JPS5837546B2 - Pattern generation method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a pattern generation method for drawing a dot pattern type figure in a display device, a printing device, or the like.

When an arbitrary figure is expressed as a set of points (dots) with fixed positions, it can also be expressed as a set of line segments, which is one set of points.

Therefore, if you can draw any line segment, you can draw any figure.

For example, the polygon 1 shown in FIG.
...Divide into 2N segments and calculate the coordinate values of both ends of these line segments.

Japanese Patent Publication No. 12706/1983 describes a technique for drawing arbitrary figures by generating a signal to follow a line segment from this coordinate data and supplying this signal to an electron beam deflection device. Ru.

According to such a technique, there is no need to calculate all the coordinates of each point within the figure 1, and high-speed drawing is possible.

However, in a Rusk scan type display device, for example, the beam deflection sequentially scans one solid surface at a constant period, so it has an image memory for one screen, and from this image memory, serial dots are printed in accordance with the beam scanning order. Since the structure is such that data is increased and supplied as a beam brightness signal, the above-mentioned technique cannot be applied.

This fact also applies to printing devices that output graphics in the form of dot patterns.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a pattern generation method that can draw figures at high speed using a low-cost display device or printing device.

Another object of the present invention is to provide a pattern generation method for generating a dot pattern representing a line segment from coordinate data at both ends of the line segment.

According to this invention, an arbitrary figure is represented as a set of a plurality of line segments having the same direction, and each line segment is determined as a combination of predetermined dot patterns.

For example, as shown in Figure 2, the coordinates (3.2) and (26
．． When drawing line segment 3 (black circle part) with 2) as both end points,
It is expressed as a combination of 8-bit patterns 4, 42, 43t44.

That is, the present invention has a display area or a printing area of n.
means for dividing a line segment into a plurality of addressed unit areas each consisting of bits, and determining an address N1 of a unit area to which this end point belongs from coordinate data of a first end point of a line segment to be drawn;
Determining the bit position occupied by the first end point within the unit area of the address N1 from the coordinate data of the first end point,
A first pattern generation circuit that generates an n-bit dot pattern in which all higher-order bits above this bit position are も1'', and this end point is determined from the coordinate data of the second end point of the line segment to be drawn. means for determining the address N2 of the unit area to which it belongs;
a second pattern generation circuit that calculates the bit position occupied by the end point in the unit area of the address N2, and generates an n-bit dot pattern in which all lower-order bits below this bit position are (11''); all bits are 1
and a third pattern generation circuit that generates a dot pattern at address (
The dot pattern generated by the third pattern generator is assigned to all unit areas from address (N1+1) to address (N21).

Hereinafter, a case will be described in which a dot pattern representing a line segment is written into the image memory (or refresh memory) of a rask scan type display device.

Now, the display area is 32 bits x as shown in Figure 2.
Considering 32 bits, an image memory with 8 bits per word and a memory with a capacity of 4 x 32 words is sufficient.

As shown in Figure 3, there are 4 words in the X direction and 3 words in the Y direction.
It is assumed that there are two words, and each word has 8 bits in the X direction.

When the coordinates of an arbitrary point within the display area are expressed as (X, y), whether this point is located at the Nb-th bit of the Nw-th word is given by the following equation.

Nw=yx4+(x/8)・・・・・・・・・・・・
...(1) Nb = x-(x/8) X 8・
・・・・・・・・・・・・・・・(2) Here ( x/8
) represents the largest integer not exceeding x/8.

For example, the line segment defined by points (3.2) and (26,2) shown in FIG. 2 is located in the shaded area shown by 5 in FIG. The third bit of , point (26.
2) are located at the second bit of the 11th word.

Therefore, starting from the 3rd bit of the 8th word, 5
The line segment shown in FIG. 2 can be drawn by writing the bit, all hits of the 9th and 10th words, and the leftmost 3 bits of the 11th word as t1'' into the image memory.

In general, any line segment is the N1th to N2th (N
It is sufficient to write "ゝゞ1" in several consecutive words up to (1≦N2).

That is, N1 is obtained by calculating equation (1) using coordinate data regarding the first end point (left side) of the line segment.

Also, using the coordinate data regarding the second end point (right side) (
1) N2 can be found by calculating the formula.

In the Nth word, a dot pattern is written in which all consecutive bits (high-order bits) to the right from the bit position determined using equation (2) are "1".

Further, in the N2th word, a dot pattern is written in which all consecutive bits (low-order bits) to the left from the bit position determined using equation (2) are "1".

Then, a dot pattern in which all eight bits are (c1'') may be written in each of the (N, +1)th word to (N2-1)th word.

FIG. 4 is a diagram showing an embodiment of the present invention.

Reference numerals 11, 12 and 13 are registers that hold coordinate data.

If we now represent the coordinates of the first end point as (X1, Y) and the coordinates of the second end point as (X2, Y), then coordinate data X1, X2, and Y are set in registers 11, 12, and 13, respectively. .

Note that these coordinate data are calculated by a coordinate data calculation section (not shown) based on the figure to be displayed.

Here, the display area is the same as 32
Consider the size of bit x 32 bits.

Therefore, each of the six coordinate data is expressed as 5-bit binary information.

The image memory 14 has a capacity of 4.times.32 words, each word having 8 bits, as explained with reference to FIG.

Therefore, each word can be specified using 7-bit binary address information.

The address conversion circuit 15 receives the coordinate data of the registers 11, 12, and 13 and calculates the address N1 of the word including the first end point and the address N2 of the word including the second end point according to equation (1).

The obtained address N0 is set in the counter 16,
Address N2 is set in register 11.

On the other hand, reference numerals 18 and 19 are pattern generators each generating an 8-bit dot pattern.

20 is an AND circuit that calculates AND for each bit from the dot patterns generated by the pattern generators 18 and 19 and outputs a dot pattern; 21 is a logic circuit in which all 8 bits are "
This is a register that holds a dot pattern consisting of 1".

The dot patterns output from these pattern generators 18 and 19, the AND circuit 20, and the register 21 are determined by the selection circuit 22.
is supplied to.

Further, 23 is a control section that controls the entire system.

Since the dot pattern output by the pattern generator 18 corresponds to the left end of the line segment, this will be referred to as LBP (left
bit pattern).

Since the dot pattern output by the pattern generator 19 corresponds to the right end of the line segment, this will be referred to as RBP (right
bitpattern).

Since one dot pattern consists of 8 bits, LB
P and RBP are shown in Figure 5? There are eight types of each.

Therefore, the pattern generators 18, 19 each have a fifth
Figure {8-word RO that memorizes dot patterns like the one shown here
It is configured with M or RAM.

In addition, the dot pattern output from the AND circuit 20 is ABP.
(and bit pattern), and the dot pattern output from the register 21 is called FBP (full
bitpattern).

Which LBP,R from pattern generator 18.19 respectively
Whether to output BP is determined by finding the bit positions of the l-th end point and the second end point from the coordinate data according to equation (2).

That is, it is sufficient to select an LBP in which "1"s continue to the right from the bit position of the first endpoint, and a RBP in which "1s" continue to the left from the bit position of the second endpoint.

By the way, by expressing the coordinate data in binary numbers, (
The calculations of equations 1) and (2) are significantly simplified.

That is, in this embodiment, the address N is the lower order of the 5-bit coordinate data Y, and the upper two of the coordinate data X.
It is represented by 7 bits arranged in a row.

Similarly, the address N2 is represented by 7 bits formed by arranging the upper 2 bits of the coordinate data X2 below the lower coordinate data Y.

Therefore, the address conversion circuit 15 only needs to perform such data rearrangement.

Furthermore, the contents of the lower three bits of the coordinate data X1 and X2 can be used as they are for the bit positions of the first and second end points, respectively, without calculating equation (2).

Therefore, pattern generators 18 and 19 are supplied with the lower three bits of the outputs of registers 11 and 12, respectively.

Next, the operation of the embodiment of the present invention shown in FIG. 4 will be explained using the flowchart shown in FIG.

In block 100, address converter 15 generates addresses N1 and N2 using the coordinate data set in registers 11, 12 and 13, and sets them in counter 16 and register 1γ, respectively.

Further, LBP and RBP are supplied to the selection circuit 22 from the pattern generators 1B and 19 according to the contents of the lower three bits of the register IL12.

At the same time, the AND circuit 20 converts LBP, RBP to ABP.
is generated and supplied to the selection circuit 22.

Next, in block 101, the control unit 23 determines the magnitude relationship between the content N1 of the counter 16 and the content N2 of the register 1l.

For example, a comparator in a control section (not shown) is used.

If the comparator detects that N1<N2, the process proceeds to block 102.

“w:xxx” in block 102 is dot pattern
This represents writing XX into the memory 14.

That is, the control unit 23 outputs a signal through the line 24 to the selection circuit 22 to instruct the selection of the LBP.

As a result, the selection circuit 22 outputs the LBP supplied from the pattern generator 18 to the memory 14.

This LBP is the content of the counter 16, that is, the address N1
will be written to.

When the processing in block 102 is completed, the process proceeds to block 103, where the control unit 23 increments the counter 16 by one.

Then, in block 104, the comparator again sets the counter 1
The magnitude relationship between the contents of 6 and the contents of register 17 is determined.

If the contents of counter 16 are again smaller than the contents of register 111, the process proceeds to block 105.

In block 105, the control unit 23 connects the FBP via line 24.
Output a signal to select.

As a result, the selection circuit 22 selects the F output from the register 21.
BP is selected and supplied to the memory 14.

This FBP is written to the address indicated by the contents of counter 16.

When the processing in block 105 is completed, the process proceeds to block 106, where the control unit 23 again adds 1 to the contents of the counter 16, and returns to block 104.

Therefore, in block 104, while the contents of counter 16 are less than the contents of register 17, counter 16
FBP is written to all addresses indicated by the contents of .

When the contents of counter 16 become equal to the contents of register 1γ, the process proceeds to block 101.

In block 101, the controller 23 connects the RB via the line 24.
A signal for selecting P is output.

As a result, the selection circuit 22 supplies the FBP output from the pattern generator 19 to the memory 14.

This FBP is written to the address indicated by the contents of the counter 16, and the process advances to block 108 to end the process.

In block 101, if the contents of counter 16 are equal to or greater than the contents of register 1γ, the process proceeds to block 109.

In block 109, the contents of counter 16 are stored in register 1.
It is determined whether the content is equal to the content of 7.

If they are equal, the process proceeds to block 110, where the selection circuit 22 supplies the ABP output from the AND circuit 20 to the memory 14, writes ABP to the address indicated by the contents of the counter 16, and ends the process. Ru.

When block 109 detects that the contents of counter 16 and register 11 are not equal, block 109 detects that the contents of counter 16 and register 11 are not equal.
1 and generates a warning signal as an error, or replaces the contents of registers 11 and 12 by a mechanism not shown and restarts the process.

As an example, the points (3,2) and (26.2) shown in FIG.
) will be explained.

Register 11 is set as X1 (ゞ0 0 01 1 (
2) "11010(2)" is set in register 12 as X2.
"cc00010(2)" is given as Y to the register 13, respectively.

The address conversion circuit 15 converts the upper 2 bits of X1 ('00'
7 hinoto OOO1000 with 5 bits of Y arranged on top of (
2)" is set in the counter 16 as N1.

Further, 7 bits 1c0001011(2)'', which is the 5 bits of Y arranged above the upper 2 bits of X2 - 11'', are set in the register 1γ as N2.

On the other hand, the pattern generator 18 has the lower 3 bits of X1
1” is supplied, so as is clear from Figure 5, LBP
A dot pattern with 5 black circles lined up as 090●●●●
● is output.

In addition, the pattern generator 19 has the lower 3 bits of X2 “01”.
0'' is supplied, so as is clear from Figure 5, RBP
A dot pattern ●●●○○Otsu○ with three black circles arranged in a row is output.

Now, when the contents of the counter 16 and the contents of the register 17 are compared, the contents of the counter 16 are smaller (block 101), so the address of the memory 14 (000100
0(2)'' (8th address in decimal notation) is written with LBP (block 102).

This is the dot pattern indicated by reference numeral 41 in FIG.

Next, add 1 to the contents of counter 16 (block 103)
, the content of the counter 16 is “O O O 1 0 01
(2)”.

Since this value is also smaller than the contents of register 11 (block 104), the address of memory 14 is ccOOO1001.
(2)” (9th address in decimal notation) is written with FBP (block 105), which is code 4 in FIG.
This is the dot pattern shown in .

Adding 1 to the contents of counter 16 again (block 10
6), (c0001010(2)”).

Since this value is also smaller than the contents of register 1γ (block 104), address “0001010 (2
)” (10th address in decimal notation) is written with FBP, and 1 is added to the contents of the counter 16.

This time, the contents of the counter 16 are "0 0 01 0 1 (2)", which is the same as the contents of the register 1γ, so RBP is written to the address of the memory 14 (cOOO1011(2)" (11th address in decimal). (Block 10
1) Finish the process.

This is the dot pattern shown at 44 in FIG.

Note that in this example, the ABP output from the AND circuit 20 is not used.

ABP is used to generate short line segments of up to 8 bits that can be drawn within one word.

For example, the line segment ○○●●●○○○ has LBP 100● axis●●●
It is obtained as a logical product with BP=●●●●●○○○.

According to this invention, if the coordinates of the points at both ends of a line segment are determined, the line segment can be easily generated, so that arbitrary figures can be displayed or printed at high speed, and especially in rask scan type display. Graphics can be displayed and printed at high speed by adding simple hardware to devices and printing devices capable of printing characters in dot patterns.

In the above embodiment, an image memory was provided since the display device was used, but in a printing device, the dot patterns obtained from the selection circuit 22 may be printed sequentially as they are or after being converted into serial data.

This may be selected as appropriate depending on the configuration of the head section of the printing device.

Further, the specific circuit for address conversion is not limited to the above embodiment, and can be modified in various ways.

For example, without using the address conversion circuit 15 shown in FIG. 4, the lower two bits of X1 and If the address conversion is performed by arranging each bit of Y in a row, it can be realized with less hardware when the display area is large.

Furthermore, an analog circuit may be used instead of the digital circuit structure as in the above embodiment.

[Brief explanation of the drawing]

Fig. 1 is a diagram for explaining division of arbitrary figures, Fig. 2 is a diagram showing an example of line segment display, Fig. 3 is a diagram of a structure of an image memory, and Fig. 4 is an embodiment of the present invention. FIG. 5 is a diagram showing a dot pattern at the end of a line segment, and FIG. 6 is a flowchart showing the operation of an embodiment of the present invention. 11, 12, 13...Register, 15...Address conversion circuit, 16...Counter, 11...Register,
18.19... Pattern generation circuit, 20... AND circuit, 21... Register, 22... Selection circuit, 23
...control section.

Claims (1)

[Claims] 1. X coordinate data X1 of the first end point of the line segment to be drawn, X coordinate data X2 of the second end point (however, X 1 < X 2)
and means for inputting Y coordinate data common to the first and second end points; dividing the display or print area in which the line segment is drawn into a plurality of unit areas each addressed by n bits; The address N1 of the unit area to which the first end point belongs is determined from the upper part of the X coordinate data X1 and the Y coordinate data, and the address N1 of the unit area to which the second end point belongs from the upper part of the X coordinate data X2 and the Y coordinate data. N2
an address converting means for calculating a first dot pattern of n bits to be allocated to the unit area of the address N1 in advance;
a first pattern memory that outputs a dot pattern of ?, which is allocated to the unit area of the address N2; A plurality of types of n-bit second dot patterns are stored in advance, and the lower part of the X coordinate data
a second pattern memory that outputs a dot pattern of 1, a third pattern memory that stores a third dot pattern in which all n bits are dot pattern and the second
a logical product means for creating a fourth dot pattern by calculating a logical product with a second dot pattern output by the pattern memory; and a logical product means for selectively outputting the first to fourth dot patterns. selecting means, when the address N is smaller than the address N2, the first and second dot patterns are assigned to the unit areas of the addresses N1 and N2, respectively, and the address (N1+1) to the address (N2 A third dot pattern is assigned to the unit area up to -1), and if the address N1 is equal to the address N2 (
A pattern generation method characterized in that a fourth dot pattern is assigned to a unit area of the address.