JPS5837575B2 - Bosenketsugousouchi - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a bus coupling device that enables independent processing systems that exchange data through one common bus to transmit and receive data by directly coupling the busses of a plurality of systems.

In information processing systems, one system is divided into several subsystems, each subsystem performs processing independently to some extent, and large problems are processed based on the processing results of each group. The system has become powerful.

In such a system, each subsystem is required to have a high degree of independence, and in order for the subsystems to work cooperatively, it is necessary to exchange data of each other's processing results.

On the one hand, the above two problems require independence of subsystems, and on the other hand, they require synchronization problems between systems for data exchange and complicated procedures for message exchange.

Further, when each subsystem is further distributed into sub-subsystems, the situation becomes even more complicated.

Therefore, each processing device is required to be multiprocessorized as described above.

We have created a coupling device that minimizes special processing procedures, minimizes the performance deterioration of each subsystem due to coupling, reduces hardware costs for coupling, and can easily increase or decrease the number of systems. We believe that providing this service is extremely effective in increasing the cost and performance of multiprocessor systems.

One conventional method for connecting systems is to connect the input/output channels of each processor and access one processor from the other as a type of input/output device.

In this method, each processor issues input/output instructions to each other, reducing speed and increasing the burden on the processors.

Another method is for one processor to directly access the memory of another processor.

This method is very ideal because the processor can access it with almost the same effort and speed as accessing its own memory.

An example of this method is called a "bus window."

In a system in which a processor and memory are connected via a common bus, the processor and memory are connected to the common bus of another system via a hardware device called ``6 bus windows'' on this common bus. On the other common bus, it acts as the master of the bus and accesses memory directly.

Although the bus window is ideal for connecting systems in this way, there are various problems in actually realizing it.

For one thing, since the window connects two independent buses, it creates contention for bus use, ie, it is necessary to simultaneously occupy two buses while the window is connected.

To solve this problem, there is a method to consider the right to use the bus and open the window after acquiring two of them.However, when there are multiple windows, if the two rights are given separately, There is a risk that a so-called "deadlock" may occur, where the window cannot be opened and stops.

Second, the window that opens is when you get the right to use two buses as mentioned above, so when one bus is in use, you are letting the other bus idle, so you cannot use the bus. Efficiency will decrease.

Thirdly, when a plurality of processors exist on one bus and use a window in common, it is necessary to prohibit the use of other processors while one processor is processing the window.

As described above, there are various problems in connecting two buses, and conventional bus windows are extremely unsatisfactory.

An object of the present invention is to temporarily buffer addresses and data using registers, solve the problem of synchronization between buses, and provide an end to signal the end of transfer as a bus control state. In addition to the status number, by giving a non-terminal status to indicate that the window is in progress, it is possible to prevent one task from being performed while another is in progress, and when the window is in the non-terminal state, the bus usage status can be changed. Immediately releasing the bus allows other processors to use the bus, resulting in efficient bus usage without deadlocks. Also, by using a comparator for the bus address, it is possible to use the bus for other processors. To provide a simple bus coupling device that can reliably transfer data without interfering with other processors' work.

The present invention will be explained below using examples.

FIG. 1 is a block diagram showing the structure of an embodiment of the present invention.

In FIG. 1, 10 indicates bus group (bus) 1, and 20
indicates bus group 2.

10L102, 103 indicate the address line group, data line group, and control line group of bus group 1, respectively; 201, 202,
203 also indicates an address line group, a data line group, and a control line group of the bus line group 20, respectively.

Reference numeral 1 designates an address storage device for inputting and setting the address line group 101.

Reference numeral 2 denotes an address comparator, which compares the address storage device 1 and the address line group 101 and outputs a match output.

Once an address is set in this address storage device 1, the contents are retained until one task is completed.
If another processor uses it or specifies a different address, the address comparator 2 will not be in a matching state and will not perform new work.

The address referred to here consists of three parts: one part is for specifying the processor that is the user, and the second part is for specifying the memory module or coupling device that is the user.
Considering that the third part specifies the intra-module address, even if the processor and coupling device become complex, it is sufficient to provide different addresses and compare the addresses all at once.

Reference numeral 3 denotes an address output device for outputting an address to the address line group 201.

Reference numeral 4 denotes a data storage and exchange device, which allows data to flow in both directions in two cases: transmission and reception.

The transmission referred to here refers to the case of sending data from the bus group 10 to the bus group 20, where the data line group 102 is input and stored, and the data line group 2
02, and when receiving, the above is the opposite.

5 is a sequential circuit, which is connected to control line groups 103 and 203.

FIG. 2 is for explaining one example of the structure of the control line group and the operation of the sequential circuit 5. In FIG.

In FIG. 2, reference numerals 103 and 203 indicate control line groups 1 and 2 corresponding to those in FIG.

STI, ACK1, NACKI, TRI, constitute control line group 1, ST1 indicates the usage status, and AC
K1 indicates a completed state, NACK1 indicates a non-terminated state, and TR1 indicates a transmitting state.

ST2, ACK2, NACK2, and TR2 similarly constitute control line group 2.

In Figure 2, one control line corresponds to each state, and when the control line reaches level "1", it is considered to be that state, but even if this assumption is made, the generality of the following explanation will be affected. Not lost.

5 is a sequential circuit and corresponds to FIG.

The operation of the sequential circuit 5 is to first consider when ST1 and TR1 become "1", which means that it is in the use state and in the transmission state, so the address storage device 1 and the data storage exchange device 4 are set, and the STI , TR1 is "1" and bus group 2 is,
The bus group 1 is set to the usage state/transmission state, and ACK is set to "1" to bring the bus group 1 to the end state, and data transmission for the bus group 1 is completed.

When ACK2 becomes “1” and bus group 2 is in the completed state,
Transmission of one data is completed.

Also, if NACK2 becomes "1" and bus group 2 becomes non-terminated, either set ST2 to "O tt", cancel the usage state, and repeat it again after a while, or set ST2 to n.
1 tt and waits for ACK2 to become "1".

If the bus group 1 is newly put into use before the bus group 2 is in the finished state, NACK1 is set to "1" to put it in the non-finished state and data transfer is prohibited.

Next, considering when ST1 is "1" and TRI is "O", it is in use state and reception state, so address storage device 1 is set and ST2 and TR2 are set to "1" and 1, respectively.
1 9 99 and bus group 2 is in use/receiving state,
NACK1 is set to "1" and bus group 1 is placed in a non-terminated state.

When ACK2 becomes "1" and the bus group 2 is in the completed state, the data storage exchange device 4 is set.

When bus group 1 is in use and address comparator 2 is in a matching state, ACK1 and NACKI are set to "1", respectively.
``O f+, the bus group 1 is brought to an end state, and the reception of one data is completed.

Furthermore, if NACK2 becomes "1" and bus group 2 enters the non-terminated state, the same operation as in the case of transmission described above is performed.

Until the processor that started reception receives data, that is, until the above-mentioned processing sequence is completed, even if 8T1 becomes "'1" and the bus group is newly in use, N'
Set 1 to kC as "1" to make it a non-terminated state.

If there is more than one person using the bus, a non-terminating state will occur.
By temporarily canceling the usage status, the bus group will no longer be occupied and "deadlock" can be prevented.

The above explanation is sufficient for the operation of the sequential circuit, but in order to understand it more clearly, it will be explained according to the timing chart of the signals of the control line group.

FIG. 3 is for showing a timing chart at the time of transmission, and the time relationship is shown by T1, T2, . . . T8.

When T1 is in use/transmission state, T2 is ACK1, TR
2, ST2 is set to "1", bus group 2 is in the use/transmission state, and bus group 1 is in the finished state.

At T3, the bus group 2 becomes unused, so it is once released from the used state and then brought back to the used state at T5.

On the other hand, bus group 1 is newly in use at T4, but since the previous transmission has not finished, it issues a non-end signal.

At T6, one data transmission ends because the bus group has reached the end state.

When bus group 1 is put into use at T7, bus group 2 is brought into use/transmission state at T8, new data is set, bus group 1 is brought to an end state, and the same sequence is repeated.

FIG. 4 is a timing chart at the time of reception, and shows the time relationship at TI, T2, . . . T9.

When bus group 1 becomes in use/receiving state at T1, NA becomes active at T2.
CK1 and ST2 are set to ``1'', bus group 1 is in a non-terminated state, and bus group 2 is in a used/receiving state.

When the bus group reaches the end state at T3, data is set and the use state is canceled.

If the bus group 2 enters the non-terminated state, it repeats the usage state until it reaches the completed state, as in the case of the above-mentioned transmission.

T4 indicates that the bus group 1 has entered a new use state, and T5 indicates that the previous data reception has not been completed, so the bus group 1 is in a non-finished state.

At T6, the bus group 1 is in use and the address comparator is in a matching state, so that the processor that has started reception is in use, and at T7 it is brought to an end state and one data reception sequence is completed.

T8 and T9 indicate that a new usage state has occurred and a similar processing sequence has started.

As can be seen from the above detailed explanation using block diagrams and timing charts, a processing system in which a number of processors according to the present invention perform processing on a common bus can be constructed by directly connecting the busses of multiple systems and performing bidirectional processing. In order to enable data transfer, an address storage device and a comparator are placed in the address line group to store addresses for specifying the processor as the user, the coupling device as the user, and the memory location. A comparator is used to compare the addresses to ensure that they do not start transferring another data during one transfer, and a data storage exchange device is installed to enable bidirectional data transfer and store addresses and data. This makes it possible to use the two buses asynchronously, and by using the in-use state, end state, and non-end state as control states, it is possible to obtain a response that data has been transferred. The object of the present invention is to provide a bus coupling device capable of generating corresponding control states when transmitting and receiving data, and operating so as not to accept other data transfers until one data transfer is completed. It is effective because it does not impair the usage efficiency of the processor, does not cause "deadlock" even when there are multiple processors and busbar coupling devices, and ensures efficient data transfer. be.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the structure of an embodiment of the present invention, in which 10 and 20 are bus groups 1 and 2, 1 is an address storage device, 2 is an address comparator, and 3 is a 4 is an address storage exchange device; and 5 is a sequential circuit. FIG. 2 is for explaining an embodiment of the control line group and the operation of the sequential circuit 5, ST1 and ST2 are in use, and ACK1
, 2 are control lines for transferring the end state, and NACKI, 2 are control lines for transferring the transmission state, forming control line groups 103 and 203, respectively. FIG. 3 is a timing chart at the time of transmission for explaining the operation of the sequential circuit 5, and FIG. 4 is a timing chart at the time of reception.

Claims (1)

[Claims] 1 an address storage device connected to two sets of bus groups 1 and 2 for transferring data, addresses, and control signals, and inputting and storing address line group 1 of said bus group 1; and said address line group 1.
a comparator for comparing the output of the address storage device with the output of the address storage device; means for outputting an address to the address line group 2 of the bus group 2; a data storage and exchange device that stores and outputs data to the other side and performs bidirectional data transfer; and a data storage and exchange device that is connected to the control line groups 1 and 2 of the bus group 1 and 2, and that the control line group 1 is in use and in the transmission state. When , the address storage device and the data storage storage device are set, the control line group 2 is put into use state, the control line group 1 is put into the end state, and the control line group 2 is put into the end state. , even if the control line group 1 is newly put into use, the control line group 1 is set to a non-terminated state, and the control line group 1
is in a use state and in a receiving state, the address storage device is set, the suppression group 2 is in a use state, the control line group 1 is in a non-terminated state, and the control line group 2 is in a finished state. Then, the data storage and exchange device is set, and only when the control line group 1 is in the used state and the comparator is in the address matching state, the control line group 1 is set to the end state, and when the matching state is not achieved, the control line group 1 is set to the end state. It is composed of sequential circuits that operate to put the bus into a non-terminating state, and connects two busbar groups, transfers data in both directions, and prevents the transfer of other data until the transfer of one data is completed. Characteristic busbar coupling device.