JPS5837576B2 - Dynamic buffer memory control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention utilizes a dynamic buffer memory control method, in particular, a plurality of buffer memories in a rotating buffer method for data transfer processing between an input/output device and a data processing device. In a data processing system, an input/output data transfer system is provided, and even if the input/output data transfer system is unable to secure the number of buffer memories instructed by others, data is transferred using the number of buffer memories actually secured. This invention relates to a dynamic buffer memory control method for controlling processing.

Conventionally, in data transfer processing between an input/output device and a data processing device, an input/output data transfer system dynamically allocates a buffer memory to control the data transfer.

In this case, a so-called alternate buffer method is generally adopted.

That is, for example, when reading data from one input/output device, two buffer memories are secured, and while the data processing device is actually reading the data buffered in one buffer memory, the other buffer memory is read.・Buffer data from input/output devices to memory,
Two buffer memories are used alternately.

However, the area where the buffer memory exists or the buffer memory is commonly used for data transfer with many other input/output devices.

For this reason, it is not always in a vacant state, and the input/output data transfer system dynamically attempts to secure a free space when actually transferring data.

Therefore, when there is little room in the area where the buffer memory exists or in the buffer memory itself, if an attempt is made to secure a plurality of buffer memories in order to use the mixed buffer method, the data transfer is undesirably made to wait.

Furthermore, once the buffer memory is secured, data transfer from other input/output devices will have to wait.

The present invention has been made in consideration of the above-mentioned points, and has an object of making it possible to deal with the case where, for example, the alternating buffer method or only a single buffer memory can be secured depending on the congestion level at the time of securing the buffer memory. There is.

Therefore, the dynamic buffer memory control method of the present invention includes an input/output device and a data processing device, and stores the data in a temporary buffer when reading data from the input/output device or writing data to the input/output device. In a data processing system that performs buffering on memory, a memory management routine is provided and a management table is provided to manage the free status of the area where the buffer memory exists, and the area where the buffer memory exists is dynamically reserved individually. The input/output data transfer system secures a predetermined number of buffer memories when transferring data between the input/output device and the data processing device, and then returns the data. It has a function of securing N buffer memories by using a first instruction to return to the buffer memory and a second command to return even if the buffer memory cannot be secured. The present invention is characterized in that when only less than N buffer memories are secured in response to a request, the data transfer is controlled to be performed using the secured buffer memories.

This will be explained below with reference to the drawings.

FIG. 1 shows the present invention at the level of program processing - an embodiment; FIG. 2 shows the control operation of the input/output data transfer system used in the invention, focusing on buffer memory management - an embodiment Flow chart is shown.

In FIG. 1, 1 is a main memory which also represents the central processing unit, 2 is a supervisor program (or its storage area) on the main memory, 3-1 to 3-4
is also a user partition and is the user's application program (or its storage area)
, 4 is the input/output data transfer system (or its storage area), and 5 is the core of the input/output data transfer system (new
7) part, 6 is a memory management routine included in the core part, and 7 is a reader included in the input/output data transfer system.
Task, 8 is also an execution leader task, 9 is also an execution writer task, 10 is also a writer task, 11
12 is a common memory extraction area, and in the case shown in the figure, the memory management routine secures the buffer memory according to the present invention in this area, and 12 to 15 are buffer memories, which are allocated at a certain timing by the memory management routine 6. What is reflected in the free space within the above area 11 at the time,
Reference numeral 16 represents an input/output device such as a card reader, 17 represents an input/output device such as a printer, 18 represents a file device, and 19 represents a management table for managing areas within the common memory extraction area 11.

Now user partition 3-4 is card reader 16
When reading data from , it is controlled as follows.

(1) When the card reader 16 is placed online, the input/output data transfer system 4 operates.

The leader task 7 and the execution leader task 8 only have a minimum number of tables until they actually operate, but when they actually operate, the control tables and input/output buffer memory 12 necessary for processing are stored in memory. A request is made to the management routine 6 in the form of a macro command such as GET MAIN.

(2) The memory management routine 6 includes, for example, the management table 1
9, it grasps the free status of the area in the common memory extraction area 11, secures the buffer memory 12 in accordance with the macro instruction, and notifies the leader task 7 of this fact.

That is, as is conventionally known, for example, if a buffer is in an empty state,
Manage memory by queuing and GET
In response to the MAIN command, the buffer memory is carved out based on FIll'O control.

Of course, once used buffer memory is released,
It is connected to the above queue and made ready for reuse.

(3) The leader task 7 uses the buffer memory 12
Once secured, the data from the card reader 16 is written to the file device 18 via the buffer memory 12.

(4) When the writing is completed, the reader task 7
The memory management routine 6 releases the buffer memory 12 and the like (FREE MAIN) according to instructions from the memory management routine 6.

(5) In this state, in response to the access to the card reader 16 from the user partition 3-4, the execution reader task issues a GETMAIN command to the memory management routine 6 as described above. A request is made to secure the buffer memory 13, etc.

(6) Once the buffer memory 13 etc. are secured, the execution leader task 8 first transfers the contents of the card reader 16 written on the file device 18 to the buffer memory 1.
Pass it to user Heartition 3-4 at the end of the 3rd passage.

In other words, the data is passed to the user partition 3-4 as if it were directly read from the card reader 16, thereby speeding up the processing.

When one of the user partitions, for example 3-4, writes data to the printer 17, the operation can be considered to be the reverse of the above, and the user partition 3-4 writes data to the file device via the buffer memory 14. Write to 18.

Data is then transferred from the file device 18 to the printer 17 via the buffer memory 15 using free timing.
Please pass it to .

However, in this case, it goes without saying that the execution writer task 9 executes the former process, and the writer task 10 executes the latter process.

The input/output data transfer system 4 operates as described above.
When using the buffer memory 12, 13, 14, or 15, a so-called alternating buffer system is adopted.

For example, data is transferred from the card reader 16 to the file device 1.
8, two buffer memories 12-1 and 12-2 are secured as buffer memories 12.

Then, while data is written to the file device 18 from one buffer memory 12-1, the contents of the card reader 16 are received by the other buffer memory 12-2.

At this time, as mentioned at the beginning of this specification, the common memory extraction area 11 is also commonly used for data transfer with other input/output devices, so if it is crowded, it is not necessarily necessary for two It is not always possible to secure buffer memories 12-1 and 12-2 together.

For this purpose, the card reader 16 to the file device 18
Data is transferred to two buffer memories 12-1 and 12-1.
2-2 can be secured.

Furthermore, even if two buffer memories 12-1 and 12-2 could be secured, data transfer with other input/output devices would have to wait.

Therefore, in the case of the present invention, for example, as the above-mentioned GETMAIN macro instruction, there are two types of GET, ie, WAIT type.
Prepare MAIN and RBTURN type GET MAIN.

The former type is a GET that waits until buffer memory is secured and then returns to the task side.
This is the MAIN macro instruction.

The latter type is a GET MI type that returns whether or not buffer memory can be secured.
This is an N macro instruction.

In addition, when securing two buffer memories 12-1 and 12-2, it may be considered that the above-mentioned GET MAIN macro command is issued twice before and after.

Then, in order to adopt a replacement buffer system, for example, the lead
Task 12 sends a buffer to memory management routine 6.
When issuing a request to secure the memories 12-1 and 12-2, the task 12 first issues a WAIT type GET MAIN macro instruction.

If there is a return from the memory management routine 6 in this state, the task 12 will store one buffer memory, for example 12
Knowing that −1 has been secured, task 12 then performs the RET
Issue a URN-type GET MAIN macro command.

And if there is one more buffer memory, for example 12-
If 2 is secured, task 12 will be 2 by alternate buffer method.
Utilizes two buffer memory.

However, if only one buffer memory can be secured, data transfer is performed using only the buffer memory IJ12-1 that could be secured.

FIG. 2 shows a flow chart of an embodiment of the control operation of the input/output data transfer system 4 used in the present invention, focusing on buffer memory management.

In the figure, a certain user partition, for example 3-4, issues a read command to the guard reader 16 (assuming the machine number is XO12), and in response, the card reader 1
6 to the disk file device 18 via the buffer memories IJ12-1 and 12-2.

Now user partition is rsTAR for read
Suppose that T READER X”0 1 2”{2F” is issued.

At this time, {2} instructs to use two buffer memories to use the alternating buffer method.

Control operations are performed as follows.

That is, (7) reader task 7 rATTACH REA
Send DER・TASKJ.

Note that A'l'TACH is a macro instruction that instructs generation of a task.

(8) As a result, the control operation performs initial setting processing from the starting point and waits for a card reader input request.

(9) Then, the leader task 7 uses the memory common management routine 6 to secure the first buffer, for example, 12-1.
A WAIT type GETMAIN macro instruction is issued to the target.

α0) If there is a return in response to the GET MAIN macro instruction, does it know that at least one buffer memory, for example 12-1, has been secured, and is the leaver task 7 instructed to use two buffer memories? Check if it is not, and if instructed, send the second Batsfa Memo lJ
Next, to secure 12-2, RETURN type GET M
Issue the AIN macro instruction.

ell) When only one buffer memory is instructed to be reserved, and when RETURN type GETMAI
If there is a return indicating that the memory could not be secured by the N macro instruction, the leader task 7 performs data transfer processing using the one buffer memory 12-1 that was secured earlier.

(121 And when the data transfer is completed, the reader
Task 7 issues a FREEMAIN macro instruction to memory management routine 6 to free buffer memo IJ12-1.

(13) As a result of the above control operation (10), if the second buffer memory lJ13-2 is secured, the reader
Task 7 has two buffer memories 12-1 and 12-2.
Data transfer is performed using

(14) When the data transfer is completed, the leader task 7 should release the buffer memory lJ13-2.
Issue the E MAIN macro instruction.

Then again, the buffer is
To free the memory 13-1, issue the FREE MAIN macro instruction.

(15) The above control operation α2 or α4)lThe above control operation is then repeated until a stop request is issued by the operator.

When a stop request is issued, the leader task r DE
T. , the CHREADER-TASKJ macro command is issued to complete the operation.

Note that DBTACH is a macro instruction that instructs task disappearance.

As described above, even if instructions are given to perform processing using the alternating buffer method, the present invention can provide the necessary number of buffers.
If at least one buffer memory can be secured, data can be transferred without waiting undesirably when no memory is available.

Therefore, even if the buffer memory area or buffer memory usage requests are crowded,
It becomes possible to perform control operations accordingly.

[Brief explanation of drawings]

FIG. 1 shows the present invention at the level of program processing - Example structure, and FIG. 2 shows the control operation of the input/output data transfer system used in the present invention, focusing on buffer memory management - Example Showing a flow chart. In the figure, 1 is the main memory which also represents the central processing unit, 2 is the supervisor program, 3-1 to 3-4 are user partitions, 4 is the input/output data transfer system, and 5 is the input/output data transfer system. The core part of the output data transfer system, 6 is the memory management routine, 7 is the reader task, 8
is the execution leader task, 9 is the execution writer task, 10
is the writer task, 11 is the common memory extraction area, 12
15 to 15 represent buffer memories, 16 a card reader, 17 a printer, 18 a file device, and 19 a management table.

Claims (1)

[Scope of Claims] 1. Data that includes a human output device and a data processing device, and buffers the data on a temporary buffer memory during data reading from the input/output device or data writing to the input/output device. In the processing system, an input/output processing system includes a memory management routine and a management table for managing the free status of the buffer memory area, and dynamically allocates and releases the buffer memory area individually. The input/output data transfer system includes a first instruction and a buffer that return after securing a predetermined number of buffer memories when transferring data between the input/output device and the data processing device.・It has a function to secure the N buffer memories by using the second command that returns even if the memory cannot be secured, and also has a function to secure the N buffer memories for the buffer memory reservation request for the N buffer memories. Dynamic buffer memory control method 92, characterized in that when only the buffer memory of is secured, the data transfer is performed using the secured buffer memory. 2. The input/output data transfer system 2. The dynamic buffer memory control system according to claim 1, wherein the buffer memory previously secured is controlled to be released after the data transfer is completed. 3 The input/output data transfer system, in controlling data reading from the input/output device, writes the data from the input/output device onto the file memory via the secured buffer memory and stores it in the user partition. In addition, in controlling data writing to the input/output device, the data from the user partition is written on the file memory and transferred to the input/output device via the buffer memory secured above. 3. The dynamic buffer memory control method according to claim 2, wherein the dynamic buffer memory control method is controlled to