JPS5837583B2 - information processing equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an information processing apparatus, specifically an information processing apparatus having an operation confirmation function.

In recent years, the capabilities and reliability of information processing devices have improved, and a single information processing device has come to be used for a wide variety of applications.

However, no matter how high the reliability has become, it is impossible to completely reduce the failure rate to zero.

Therefore, as the use of information processing devices becomes more sophisticated and the scope of their influence expands, there is an increasing need to be prepared in the unlikely event that an operating information processing device should fail.

The first thing that must be done to deal with a failure in an operating information processing device is to detect the failure.

From the above background, various techniques have been developed for detecting failures during operation of information processing apparatuses.

Typical examples are shown below. (1) Successively compare processing results by duplicating devices or circuits.

(Smell) The information in the information processing device is represented by a code with redundancy, and the hardware constantly performs checks that utilize this redundancy.

(3) Inspect using a test program to confirm the operation within the information processing device.

Item 1 above duplicates each device or circuit block within the device, performs the same processing on them, constantly compares the processing results, and if they match, the device or circuit block is duplicated. This is to confirm that it is working correctly.

In addition, the second term applies to parity checks, residue checks, one-out-of-N checks of control signals, etc.
Parity checks for data transfer paths such as memory can be implemented at relatively low cost.

However, when applied to logical operation circuits, control circuits, etc., the cost becomes relatively high.

Item 3 has various variations depending on the method of starting the test using the test program, the operating level of the test program, the storage location of the test program (at all times and during test execution), etc.

Typical variations of microprogrammed information processing devices are that the test is started by human intervention and instructions, or automatically by system software or hardware timers, etc. at approximately fixed intervals. There is something.

The operation level of the test program includes a software program level (instruction level) and a microprogram level.

Furthermore, regarding the storage location of the test program, there are storage media such as magnetic tape that requires manual operation to start the test, storage on a magnetic disk as part of the system software, and storage as part of the main memory or control memory. There are things that are stored in .

Furthermore, if the storage location of the test program is different between when the test is executed and when the test is executed, variations also occur depending on the means for moving the test program for executing the test.

Additionally, in addition to the items listed in (1), (2), and (3) above, there is also a typical method that processes and records information with redundancy in the software that uses the information processing device. Alternatively, there is a method of performing the same information processing twice using different processing procedures and comparing the results to confirm the results using software.

The reason why the various techniques described above coexist is that each method has its advantages and disadvantages, and the points required of the failure detection technique differ depending on the information processing system to which it is applied.

The most basic points are as follows.

l. Elapsed time required from failure occurrence to failure detection2. Increased hardware cost for fault detection 3. Processing capacity of the information processing device (storage capacity and device exclusive time) consumed for failure detection 4. Completeness of failure detection (failure detection rate) If we evaluate the above points using, for example, a method of duplicating equipment and constantly comparing and inspecting its output, we find that the elapsed time required for failure detection is virtually zero, which is the most It is short, and the hardware cost is doubled due to duplication, and it is necessary to add a comparison circuit, so it is the most expensive, and there is almost no loss in processing capacity (because the two information processing devices operate synchronously, For comparison purposes, the vehicle will be operated more slowly than when operating alone.

), it can be said that failure detection is almost perfect.

That is, this method does not allow false information to occur, even if the probability is very low, because false information resulting from a failure will immediately have irreversible consequences.

This technology is suitable for use in systems such as ``.

Furthermore, in the case of an information processing device used in a batch processing system, if the occurrence of a failure is detected within 10 seconds, the erroneous information issued by the information processing device can be recovered with sufficient certainty, so the time required to detect the failure is shortened. It doesn't need to be any shorter,
The more important point is that the cost for detection including the above (2) and (3) is lower.

It is natural that complete failure detection is desired in any system, but it is difficult and extremely expensive to detect 100% of failures using just one method.
Since the probability of failure occurrence is extremely small, several failure detection methods are usually used together to improve the completeness of failure detection, and the failure detection rate of each individual failure detection method is equal to the failure detection rate for the above failure detection. It is viewed and evaluated from the perspective of trade-off with cost.

Then, the overall fault coverage rate that combines multiple fault detection methods and its fault detection cost are evaluated as a trade-off between the probability of fault occurrence and the adverse effects caused by erroneous information caused by the fault.

Therefore, several fault detection technologies have been developed that have characteristics for each of the four points mentioned above.
They are still in use today.

The present invention has been made in view of the above background, and corresponds to the inspection using the test program in the above-mentioned item 3, and includes a dedicated memory and a control circuit for detecting abnormality in the processing device, and detects idleness of the processing device. An object of the present invention is to provide an information processing device whose reliability is improved by inspecting the processing device based on commands from a dedicated control circuit when the device is idle (idle).

Another object of the present invention is to provide an inexpensive failure detection technique that can be widely applied to many information processing systems.

This technique requires a sufficiently short time to detect a fault, has low hardware costs, does not consume the processing power of an information processing device for fault detection, and has a satisfactory fault detection rate.

The present invention will be explained in detail below.

First, an overview of the present invention will be explained, focusing on the case where the present invention is applied to a central processing unit (hereinafter referred to as CPU).

Since fault detection using a test program necessarily operates the information processing device to execute the test program, a portion of the information processing capacity is required for fault detection.

The present invention is no exception to this, but the test is performed using time that is not being used effectively by the user of the information processing device, and from the user's perspective, the time that is wasted for fault detection is reduced. One of the features of the present invention is that the information processing time is almost zero.

It has a dedicated storage device to store test programs.

When operating to detect a failure, the test program is read word by word from the storage device and the test is executed.

Therefore, there is no need to perform extra work such as moving the test program to a part of the control memory prior to test execution or restoring the control memory after the test is completed.

Furthermore, since the test program is stored in a storage device exclusively used for operation confirmation tests (hereinafter referred to as dedicated memory), there is no need to maintain a space for storing the test program in the control storage device.

In order to reduce the storage capacity of the dedicated memory, the test program is not directly stored in the dedicated memory in the form of microinstructions, but is stored in the form of the address of the microinstruction (or the first microinstruction of the microroutine) in the control storage device. One of the features of the present invention is that it is designed to

In the embodiment of the present invention, the bit length of the microinstruction is 80.
The capacity of the control memory for storing microprograms is 8K words.

Even in the case of an embodiment in which the dedicated memory is summarized in the form of diagnostic commands (Fig. 5) so that 8K words of control memory can be accessed and there is a margin so that the control circuit etc. can be used for other purposes. Since only 16 bits are required, the storage capacity of dedicated memory is 1/5 compared to storing microinstructions as they are.
It becomes.

Next, an outline of the present invention will be explained regarding the four points mentioned above.

The time required from the occurrence of a fault to the detection of the fault varies depending on the operating status of the system to which this fault is applied, but is usually between several milliseconds and several hundred milliseconds.

This means that the operation can be checked while the CPU is waiting for input/output, and the details will be described later.

Further, hardware that is increased for failure detection includes a dedicated memory and its address register.

Also shown as a circuit for operation confirmation test (Figure 3)
However, except for the dedicated memory and its address register, hardware for fault diagnosis can be used as described below.

Further, the processing time of the CPU consumed for fault detection is almost nil because idle time for waiting for input/output is utilized as described above.

As for the capacity of the control storage device dedicated to failure detection, there are some microprograms created for failure detection.

"Saving general registers" referred to in the test result accumulation routine in Figure 8 and the flowchart in Figure 4
The "test initialization routine" and "general register restoration" routines (none of these routines are shown), the middle part of the flowchart in Figure 4 (compared with the DIS instruction flowchart in Figure 2), (increased portion).

Since each of these routines has a small amount, the amount required is, for example, about 1 to 3 yen of the storage capacity of the control memory.

Finally, the completeness of failure detection is greatly influenced by the logical structure of the hardware of the information processing device to which the present invention is actually applied, the microinstruction words, and the design of the operation confirmation test written in the dedicated memory. .

This is similar to the case of failure detection using the conventional test program method.

Judging from the results of conventional test programs and the embodiments of the present invention, generally speaking, a fault coverage rate of about so% can be easily achieved, and it is not that difficult to obtain a fault coverage rate of about 95%. .

To summarize the outline of the present invention described above, when the CPU enters an idle state due to waiting for input/output, etc., an operation confirmation test is carried out that is stored in a dedicated memory in the form of specifying the address of the pedestal memory. ``By doing so, the advantages of the conventional fault detection using a test program at the 6 microprogram level'' can be utilized, and the disadvantage of the conventional method, ``processing power is consumed for testing.''
and "Large storage capacity for storing test programs" have been significantly improved.

” can be said. Hereinafter, details of embodiments of the present invention will be explained using the drawings.

FIG. 1 is a conceptual diagram showing a CPU to which the present invention is applied, simplified to the extent that the relationship with the present invention can be made clear.

The microprogram that controls the CPU is stored in the fork storage device 1.
The microinstruction word read out according to the address given from the sequence control section 2 enters the microinstruction register 3 and controls the sequence control section 2 and other parts of the CPU as a microinstruction.

The other part shown in FIG. 1 is the arithmetic unit.

Inside the arithmetic unit A, there are a general register GR5, a scratch pad memory SPM6, a working register RT7, and an operand register RD8, which are connected via two selectors 9 and 10 to two inputs of an arithmetic logic circuit ALU11.

Since the arithmetic logic circuit ALU11 is generally well known as a circuit that performs binary operations, decimal operations, logical operations, shifts, etc., the explanation thereof will be omitted.

The output of the logic operation circuit ALU11 can be written to the general register GR5, scratch pad memory SPM6, working register RT7, and operand register RD8 again.

Further, 12 is an indicator, and the logic operation circuit AL
FZ and FN, which are set when the output of U1 1 is numerically zero or negative, and logic operation circuit ALU
1 F that stores the carry resulting from addition within 1
It consists of three flip-flops of C.

The general register GR5 is a general term for registers visible to software, and the indicator 12 is also a register visible to software, but as described below, it is also used for control in the present invention and is treated separately.

Further, an input data path for setting the operand read from the main memory is also connected to the operand register RD8, but this is not shown.

Information necessary for sequence control is sent from each part of the CPU to the sequence control section, and the sequence control section determines the address of the next microinstruction word to be read based on the microinstructions and their information.

FIG. 3 is an example in which the present invention is applied to the CPU shown in FIG.

In the figure, a selector is added so that the address information of the control storage device is not only given from the sequence control section but also from the command register in the operation confirmation test circuit.

(In actual design, the amount of hardware increase will be smaller if the sequence pedestal is modified to include this selector function.

In the description of the present invention, a case will be described in which a selector is newly installed in order to simplify the description and avoid going into the sequence control section that differs for each individual application.

) Since the CPU is the same as that shown in FIG. 1, the numbers and abbreviations of each block will be the same, and detailed explanation will be omitted.

As a hardware block added to FIG. 1, there is an operation confirmation test circuit 20.

The circuit 20 has a dedicated memory 21 of 16 bits x 512 words and a 9-bit address register 22.
The output of 1 is sent to the command register 24 via the selector 23.
connected to.

The output of the command register 24 is used as the address information of the above-mentioned *+m storage device 1, and is also used as the address information of the dedicated control circuit 2.
7 controls the entire operation confirmation test circuit 20, and can also instruct reading/writing of registers in the CPU.

(Refer to Figure 6 Types of Commands) The contents read from the register in the CPU can be set in the data register 25 via the selector 23, or any data can be set in the data register 25 and transferred to the register in the CPU. A data path 26 is provided so that the number can be written.

In addition to the registers shown as the arithmetic unit ALU11, the registers in the CPU include a mode register (not shown) that determines the operating mode of the CPU (normal mode/l-instruction move l-step mode).

In addition, since the command register 24, data register 25, dedicated control circuit 27, etc. are also used for fault diagnosis, an external device interface 28 is provided to the command register 24 and data register 25 so that diagnostic commands can be sent from external devices. Command register 2 via the selector 23
4. Connected to the data register 25.

Further, the address register 22 of the dedicated memory 21 has a count-up function.

Furthermore, along with the registers in the CPU, a dedicated memory 21 and an address register 22 are connected to a data register 25 so that they can be written to from the outside, and are used for purposes such as fault diagnosis and loading of the test program of the present invention into the dedicated memory 21. used in

FIG. 5 shows the format of the command.

The command consists of 16 bits and is stored in the command register 24.
and the dedicated control circuit 27 is designed to be able to accept this command format.

That is, 3 bits for the command part and 1 bit for the address part.
It has 3 bits, can address up to 8K words of the poison storage device 1, and can specify 8 types of operations.

FIG. 6 is written about the types of commands, and shows how the 13 bits of the address part in FIG. 5 are used depending on the type of command.

When the command code "0" is given, the CPU is instructed to start executing the microprogram from the address specified by the 13 bits of the address field.

Furthermore, when the command code "l" is given, the CPU is instructed to read the microinstruction word from the address specified in the address field and execute it.

"Step CPU command" with command code "l" is "start CPU command" with command code "'O"
The difference is that in the case of a step CPU command, if the CPU executes one step, the
The point is to force U to stop its operation.

To achieve this, upon receiving the "step CPU command", the dedicated control circuit 27 only needs to send a control signal to the CPU that forces the CPU's mode register to be in the 1-step mode.

As will be described later, when executing the test program according to the present invention, the mode register is first set to one-instruction mode.

As a result, the microprogram started with the ``start CPU command'' is executed until the ``END'' microinstruction representing the end of the microroutine, at which point the CPU is stopped.

Then, “Star}CPU command” and “Step CP
When the U command is executed, the execution is finished and C P
'The next command is stored in the dedicated memory 21 until the U stops.
A dedicated control circuit 27 is designed to wait for reading from.

Further, when the dedicated I1 leg circuit 27 receives the "stop test command" of the command "'2", it stops reading out the command from the dedicated memory 21 and enters a standby state.

Since it is easy for engineers involved in electronic computer design to realize this using logic circuits, a dedicated control circuit 2
Details of T are not shown.

Incidentally, a "start test" microinstruction is given from the macroinstruction register 3 to the dedicated control circuit 27.

"Start test" is a microinstruction that instructs the dedicated control circuit 27 to start a test of the present invention.

Hereinafter, the operation of the present invention will be explained in detail.

First, the operation of the CPU to which the present invention is applied, that is, the operation of FIG. 1 will be explained according to the flowchart of FIG. 2.

In the figure, instructions 1 to N are machine language instructions of the CPU from the software perspective.

When an instruction 1 is given to the CPU as a machine language, the sequence f6sp unit 2 decodes the instruction code part of the machine language and stores the address S1 of the control storage device 1 where the starting address of the microprogram of the instruction 1 is stored in the control memory. feed into the device.

The corresponding microinstruction is read out and placed in the microinstruction register 3, and the CPU operates according to the microinstruction, calculates (adds) the general register GR5 and the operand using the logic operation circuit ALUII, and then writes the general register GR5 and the operand again. Write to register GR5.

In the case of this instruction l, all the operations of the instruction l are completed by executing the microprogram l step, so
The microinstruction "END" is also executed at the same time in step S1.

The microinstruction "END" performs various operations associated with the completion of processing of one instruction word.

For example, if a one-instruction mode of operation is specified in the mode register, the CPU is stopped by the microinstruction "END".

Also, the microinstruction “END” is sent to the sequence control unit 2.
It has the function of instructing the control storage device 1 to give the start address of the microprogram of the next instruction word as an address.

Therefore, a program that executes instruction 3 after instruction l [
If so, the sequence leg unit 2 sets the address S5 in the control storage device 1 of the microprogram starting address corresponding to the instruction code of the next instruction word (instruction 3) to ilJ.
Ml storage device 1.

In this way, next microstep S is executed.

Then, under the control of the microprogram, S, . S6
In S7..., the microinstruction is executed.

Since microprogram control itself is well known, illustration of the contents of individual microsteps is omitted in FIG.

The end of the microprogram consisting of steps S7tSg*S and the branching of the microprogram at step S18 are illustrated.

One of these instructions is the DIS instruction.

This instruction puts the CPU into an idle state until it receives some kind of signal from the CPU, such as an input/output interrupt.
This is a command that has the function of rubbing.

The operating system executes this DIS instruction when the CPU waits for the completion of an input/output operation and there is no more work to be done by the CPU.

Since this DIS command is used as a means for starting a test program (hereinafter referred to as an operation confirmation test program) in the present invention, a flowchart is shown in FIG.

When the DIS instruction is executed, the microstep S18 is executed as described above, and the control flip-flop FDI
S is set.

This flip-flop FDIS controls operations specific to the DIS command, such as controlling an operation indicator lamp on the operator panel, and is not shown because it has no direct relation to the present invention.

Next, in step 814, a loop waits for the XIP signal indicating the presence of an input/output interrupt from the CPU column section to become ""1".

While staying in this loop, the CPU is idle, doing nothing.

Eventually, when one of the input/output operations is completed, the XIP signal becomes
1'', the program proceeds to step S15, resets the FDIS, and then proceeds to a processing routine necessary to complete the input/output operation.

If the XIP signal is "L" when the microinstruction "END" is issued after the processing of one instruction is completed, the sequence control unit 2 stores the starting address of the next instruction's microprogram in the control storage device 1. Instead of giving this, the start address of the interrupt processing routine can also be given to move to the interrupt processing routine.

FIG. 4 is a flowchart of the DIS instruction after applying the present invention in its simplest form.

The portion surrounded by broken lines has been added to the flowchart of the DIS instruction in FIG.

As mentioned above, in the CPU of the application example of the present invention, it is certain that the CPU is in an idle state while executing this DIS instruction, so when the DIS instruction is entered, the operation confirmation test of the present invention is carried out. This is what I did.

When the DIS command is entered, the FDI S
Set.

Next, test whether the function confirmation test is prohibited,
If it is prohibited, the flow is exactly the same as before.

This is to prevent some diagnostic programs from performing function confirmation tests in order to maintain compatibility with conventional ones, and is also for processing after a parity error in the dedicated memory 21 is detected. Yes, but it's not essential.

Normally, the test is not prohibited, so the routine proceeds to save the general register.

This is to store the contents of the general register GR5 in a predetermined area in the scratch pad memory SPM6 so that the general register GR5 visible to the software can also be freely tested in the operation confirmation test.

Further, the contents of the indicator 12 are also stored in this routine.

Next, the test initialization routine is entered, and registers such as the general register GR5, the working register RT7, and a portion of the scratch pad memory SPM6 are initialized to have certain values prior to the test.

Also, registers related to the pedestal (not shown), which should be initialized by a microprogram, are also initialized here.

(As described later, this embodiment also uses commands to initialize control relationships.

) Note that saving the general register and initializing it for testing are both means commonly used in test programs at the microprogram level, so detailed explanations will be omitted.

The preparations for starting the operation confirmation test are now complete.
Next, we move on to the step of issuing the microinstruction ``start test'' to perform an operation check test.

The microinstruction 6 "start test" is sent from the microinstruction register 3 to the dedicated control circuit 27 as shown in FIG.

The dedicated control circuit 27 first uses the dedicated memory address register 2.
2 to zero, read the start address of the operation check test program from the dedicated memory 21 and select it from the selector 23.
is input into the command register 24 via the .

On the other hand, on the CPU side, after issuing the microinstruction "start", the CPU stops as shown in the flowchart of FIG.

If the microinstruction set has a microinstruction that stops the CPU, or if the macroinstruction "start test" newly established for this invention can also have the function of stopping the CPU. , it is easy to stop the CPU at this point.

In the embodiment of the present invention, the design concept is such that the microinstructions used for internal control of the CPU do not have the function of stopping itself (CPU), so the CPU is stopped using commands read from the dedicated memory 21. .

Then, in the microprogram of the DIS instruction, after issuing the microinstruction 6 "start test", we actually put a microstep that unconditionally jumps to its own address 5, and then execute C
I am trying to wait for the PU to be stopped.

The remaining portions of the flowchart of the DIS command in FIG. 4 will be explained later after the explanation of the operation confirmation test program is completed, and the explanation will move on to the explanation of the operation confirmation test program in FIG. 7.

FIG. 7 shows an example of the configuration of the operation confirmation test program in the dedicated memory.

As mentioned above, the first command read from the dedicated memory 21 is the "step CPU command" stored at address zero in the dedicated memory.

The function of the "step CPU command" consists of two things: starting the CPU from a specific microstep and stopping it after executing the l step, but as mentioned above, the CPU is not yet stopped at this time. Therefore, the first function does not work and only the second function works, which is used as a means for the above-mentioned command (to stop the CPU).

Now, after reading the "step CPU command" from address 0, the dedicated memory address register 22 is counted up, and when the execution of the "step CPU command" is finished, the data is next read from address 1 of the dedicated memory 21 to the mode specification register. A "data write command" for writing is read out and set in the command register 24 in the same manner.

Here, the dedicated control circuit 27 decodes the command code and learns that data follows, reads address 2 of the dedicated memory 21, and sends it to the data register 25 via the selector 23.
Put it in the left half of

Note that the data register 25 has a word length equivalent to two words of the dedicated memory 21, so in the case of a normal "data write command", the second address following the command in the dedicated memory 21 is stored in the data register 25. , when the word length of the register 25 to which data is to be written is short, data reading is terminated after one word in this way.

The data stored at address 2 is such as to set the mode register to the one-instruction mode, so when the dedicated control circuit 27 executes this command next time, the CPU enters the one-instruction mode.

The purpose of this is to make the CPU execute a specific microprogram routine, as will be described later, and to prepare for stopping the CPU when the execution of that routine is finished.

Next follows a series of ``data write commands'' to initialize control-related registers and flip-flops for testing purposes.

The contents vary depending on the design of the test to be performed later and the logical structure of the information processing device to which the present invention is applied.

In the embodiment of the present invention, a CP has a function of resetting a large number of control registers and flip-flops at once.
Since it is U, a virtual register address is given to the reset function, and the reset function is activated by a "data write command", thereby simplifying the initialization procedure.

When the initialization for the test is completed in this way, the test itself for detecting a failure begins to be executed.

The content of this test varies depending on the logical structure of the information processing device and the design of the operation confirmation test, and can be easily deduced by engineers who have experience in writing test programs at the microprogram level. Therefore, the mechanism for executing the test will be mainly explained below, and the details of the test will not be explained.

First, the command “Start CP” at T1,1 in Figure 7
U, S2j is read and executed.

As a result, the CPU executes the microprogram starting from address 82 in control memory 1, executes the microinstruction "END", and stops.

In other words, referring to Figure 2, this! It can be seen that this is equivalent to starting from a state initialized for the 2 test and executing instruction 2.

The microprograms S2, S3, and S4 of instruction 2 each perform some processing on the states of registers, memory, and flip-flops in the CPU, and store the results.

If there is a failure in the processing circuit, register, memory, or flip-flop (hereinafter referred to as a register) used at this time, and the data used at this time meets the conditions that make the failure obvious, then the failure is This means that the information stored in the register is influenced and changed by certain things.

The affected information may be read out further in a subsequent step and stored in another register or the like or in the same register.

In any case, is this step supposed to cause a difference in the information stored in registers etc. depending on the presence or absence of a failure? The microstep sequence executed here is selected from the control memory 1 from this point of view.

When the microprogram progresses to 84 and completes its execution, the CPU, which is in the l-instruction mode, stops.

Then, the dedicated control circuit 21 knows that the CPU has stopped and starts the next T.
Read and execute commands 1 and 2.

Since this is a "step CPU, S8 command", the CPU then executes the fourth microstep of instruction 3 by one step, as shown in FIG. 2, and then stops.

Then, the dedicated control circuit 21 further reads and executes the next command "Start CPU, S20J.

As a result, the CPU executes a microstep sequence consisting of three steps S20tS21 and S2 and then stops.

In this way, each part of the CPU is operated one after another, and the results are stored in registers, etc., or further processing is performed based on the information thus stored, and the results are stored in registers, etc. After repeating, dedicated control circuit 2
1 reads and executes the command "Start CCPU.S,l" of T1,n.

S here.

is the starting address of the test result accumulation routine shown in FIG.

FIG. 8 shows an example of a test result accumulation routine, which was created for the present invention and is stored in the control storage device 1 along with the routines shown in FIG.

The purpose of this routine is to collect the processing results stored in various registers in the CPU as a result of previous tests, and if even one processing result is affected by a failure, it is guaranteed that there is no failure. The goal is to compress the amount of data by creating a single word that takes a value different from that obtained in the previous example.

Considering that the purpose of the present invention as a whole is to detect faults and there is no need to localize faults, in the case of the embodiment of the present invention, the test results are compressed and simplified to one word data.

Furthermore, as a data compression method, binary addition is used, and the carry generated at that time is added to the least significant digit during the next binary addition.

The CPU is equipped with hardware like this for the convenience of multiple-precision operations.

The test results are stored in a specific address (TSA) of the scratch pad memory SPM6, and the TSA address is not accessed at least during the operation confirmation test except in this test result storage routine.

This TSA address is initialized by the test initialization routine shown in FIG.

Now, the "start CP" at address T1, n of the dedicated memory 21
When the "U, SC command" is executed, as shown in Figure 8, the working register RT7 and flip-flop F
The test results left in C are the scratchpad memory S.
It is added to the contents of the TSA address of PM6, and the result is stored in working register RT7 and flip-flop FC.

Next, the test result left in the O register of general register GR5 is added to working register RT7, and the carry generated in the previous RT+SMP (TSA) operation is added via flip-flop FC, and the result is is again stored in working register RT and flip-flop FC.

In this way, the test results are compressed into one word, and at the end, you can write down the results as a scratchpad memo! After writing to the TSA address of JSPM6, the accumulation of test l results is completed, the CPU stops with the microinstruction "END", and the dedicated control circuit 27 reads and executes the next command at address T2,1. Then, test 2 starts.

Incidentally, setting/resetting the flip-flop FZ does not have much meaning at this stage, and details will be described later.

In the embodiment of the present invention, in order to reduce the amount of test data occupied in the dedicated memory 21, the test registers are initialized only before the execution of test t-1, and from test 2 onwards, the previous test Efforts are being made to design the next test using the information left in registers, etc., but there are many cases where it is difficult to do so. A "data write command" is often executed first among several commands.

When test 2 is completed, the test result accumulation routine shown in FIG. 8 is executed again by the command at address T2tm, and the result of test 2 is added to the accumulated results of test l stored in address TSA of scratchpad memory SPM6. , is again compressed into one word and stored in the TSA address of the scratch bat memory SPM6.

In this way, tests up to test M are executed one after another.

In the test M, the working register RT7 is left idle, and after the test I-M is finished, the complement of "the correct value obtained by compressing the test results of all tests" is written into the working register RT7 using a data write command.

(Here, the correct value means the compressed test result when there is no failure.

) The data to be written to working register RT7 requires two words of dedicated memory 21.

Then, the test result accumulation routine shown in FIG. 8 is executed again.

As a result, all test results from test 1 to test}M are compressed into one word, and if there is no failure in the CPU (in this case, the final addition result is zero).

That is, the presence or absence of a failure in the CPU is stored in the form of whether the flip-flop FZ is set or not, and if there is no failure, FZ is set.

In addition, in the embodiment of the present invention, as mentioned above, the last test, Test M, is treated as a special number, and the complement of the correct answer value is added in the process of data accumulation. This is a means to reduce it.

Figure 7-A is a modification of the operation confirmation test program in the dedicated memory in Figure 7, and as shown in this figure, the test}1
By separating the accumulation of test results up to test l-M and the comparison with the correct value, the design becomes simpler and the restrictions placed on test M can be removed.

In that case, there is no need to set the flip-flop FZ at the end of the accumulation routine; instead, the correct value is compared with the accumulated result, and if it matches the correct value, the flip-flop FZ is set.
Step Sj of setting and resetting if they do not match.
Is required.

Step Sj can be easily found in a microprogram for executing instructions, so it can be used.

FIG. 8-A shows the test result accumulation routine and determination step that have been modified in this way.

This essentially completes the failure detection and begins post-processing.

First, execute the "data write command" to return the mode register, which was rewritten to 1-instruction mode for testing, to normal mode, and then "Start cPU, Sd
Execute a command.

This step Sd is the address of the microinstruction written to be executed next to the "stop" step in the DIS instruction flowchart in FIG.
By executing the "Sd command", the execution of the microprogram of the DIS instruction shown in FIG. 4, which was interrupted for the operation confirmation test, is resumed.

When the dedicated control circuit 27 decodes the next "stop test command", it stops reading the dedicated memory 21 and returns to the standby state.

Now, as described above, the CPU microprogram resumes execution from the step at address Sd in FIG. 4, and first tests the flip-flop FZ.

If the flip-flop FZ is zero, it means that a failure has been detected as described above, so the process proceeds to the example sequence processing routine and reports the occurrence of an abnormality in the same way as other example fault processes.

If the flip-flop FZ is set, the contents of the general register GR5 saved in the scratch pad memory SPMS are read out, and the general register GR5 and the indicator 12 are restored.

This means that all the post-processing for the operation check test has been completed, and the process enters a loop waiting for a human output interrupt signal, as in the case of the conventional DIS command.

Since the explanation of the operation of the embodiment to which the present invention is applied in the simplest form has been completed above, the explanation of the operation confirmation test and the test result accumulation routine will be supplemented to some extent.

As shown in the example of FIG. 7, test results are accumulated after several steps are executed.

■The reason why test results are not accumulated every time a step is executed is as follows.

(1) If the number of commands for executing the test result accumulation routine increases, the overhead will increase both in terms of the time required for the test and the number of words in the dedicated memory.

(2) As a result of the test, it is usually not possible to store the contents of all registers, etc. in the storage routine.

Therefore, as a result of executing a certain microinstruction or a sequence of microinstructions, information stored in a register etc. that cannot be seen by the accumulation routine is processed by executing another microstep or sequence of microsteps, and the information is stored in a register etc. that is not visible to the accumulation routine. It is necessary to guide it to a visible register, etc., and then execute the test result accumulation routine.

(3) Normally, when only one microstep sequence is executed, the processing results are stored in only a portion of the registers etc. that are visible to the accumulation routine.

Therefore, it is necessary to execute a microstep or a series of microsteps that store processing results in different registers.
Testing can be carried out efficiently by executing the test result accumulation routine after the processing results have been stored in the registers, etc.

The test results show that the accumulation routine uses binary addition to return the carry to the least significant digit, so fI? There is no need to worry about the same processing result being accumulated multiple times, except for the most common cases.

(If exclusive OR is used instead of binary addition, it is necessary to design the operation confirmation test with strict care so that the same processing result is not accumulated an even number of times.

) In the case of the present invention which uses binary addition, it is necessary to avoid storing the processing result and its complement together with the processing result to be stored.

When a certain processing result and its complement are accumulated together, the effect of the fault included in the processing result is canceled out, and the effect of the presence of the fault no longer appears on the accumulated result.

Similarly, there is no need to be concerned about a failure affecting multiple processing results, but if a failure affects two processing results in such a way that they are exactly complementary to each other, After all, the influence of the failure no longer appears in the accumulation results.

If it is difficult to avoid such complementation problems in the design of the operation verification test, change the accumulation routine and
This problem can be solved by changing to a more advanced data compression method, such as rotating and shifting the accumulated results up to that point and then adding them.

In addition, in Embodiment C of the present invention, in order to reduce the amount of data occupied in the dedicated memory as much as possible, the presence or absence of a failure is not determined for each test so that there is no need to have a correct value for each test.

However, if necessary, design the operation confirmation test so that the accumulated results are zero for each test, or have a correct value for each test, and determine whether there is a failure at the end of the test result accumulation routine. It is easy to modify the present invention in different ways.

The present invention is useful for detecting failures in parts such as arithmetic circuits and control circuits where parity checks cannot be performed efficiently.

On the other hand, failures can be detected efficiently based on hardware redundancy checks such as parity checks for register files, memories, and surrounding data buses.

Therefore, we divide the entire information processing device into a part for which failures are detected by checking redundancy and a part for which failures are detected by the present invention, and limit the operation confirmation test to the latter part (including the interface with the former part). This reduces the amount of operation confirmation tests and reduces the storage capacity of dedicated memory.

For example, when a number of registers are grouped together using an integrated circuit in a register file, testing the operation of each register individually will require a large amount of testing, but parity checks of the register file and the data paths before and after it If you design the hardware to do so, and in the operation confirmation test, you are responsible for detecting failures in the addressing circuit of the register file and the data circuit connected to the parity-checked part, the amount of testing can be significantly reduced. .

In the above description, the main subject has been an arithmetic section that can be directly controlled by microinstructions, but it will be shown below that the present invention can also be applied to a section within a CPU that is under hard-wired control.

For example, in the example shown in Figure 3, the instruction code of the instruction to be executed first in the sequence control unit is decoded, the start address of the microprogram for that instruction is prepared, and the microinstruction ``END'' is waited for. The circuit is hardwired control.

To test this part, l. Next, write the instruction word to the register containing the instruction word to be executed using the "data write command".

2. Test some arithmetic unit using the "step CPU command".

At this time, each part of the hard-wired control also performs one step of operation at the same time, so the register containing the starting address of the microprogram for that instruction is entered.

3. It is sufficient to execute a step such as moving the contents of the register to a register visible from the storage routine.

That is, the test can be performed by setting registers and the like for testing and running the CPU only by the necessary steps.

Next, the amount of time required from the occurrence of a failure to the detection of a failure in the present invention will be described.

Due to the nature of the operation confirmation test of the present invention, this required time basically depends on the frequency at which the CPU waits for input/output, and this frequency depends on the frequency with which the CPU to which the present invention is applied is installed in any information processing system. It changes significantly depending on various factors, such as the amount of data and the nature of information processing, and even a single system changes from moment to moment.

Therefore, in the case of the embodiment, prior to applying the present invention, the frequency at which the CPU waits for input/output was investigated using several system configurations and under various load conditions.

As a result, it was found that even when there are many jobs that are close to CPU bound, the CPU is in an input/output state once every several hundred milliseconds.

Also, there are two types of input/output waiting time: waiting for disk seek and data transfer, and waiting for input/output, which means waiting for input of a new job or waiting for operator action, and there is no big difference between the two. However, we found that the above conclusion remains the same even if we focus only on waiting for human output for 1 millisecond or more.

That is, when the present invention is applied to the information processing device, it is found that an operation confirmation test is performed once every several hundred milliseconds, and in the present invention, the time required from the occurrence of a failure to the detection is shorter than that of a normal system. It turned out to be much shorter than needed.

However, since this value is expected to vary significantly depending on the individual case of the information processing apparatus to which the present invention is applied, it is necessary to conduct the above-mentioned investigation for each case when applying the present invention.

Next, various modifications of the present invention will be described. First, as a first modification, in the DIS instruction flowchart of FIG. 4, the test initialization routine is executed only once before the operation confirmation test. However, depending on the logical structure of the information processing device to which the present invention is applied and the design of the operation confirmation test, the test initial set using this microprogram may be used at the beginning of each of Tests 1 to M shown in FIG. You may want to run a conversion routine.

In that case, this initialization routine can be removed from the flowchart in Figure 4 and made independent like the accumulation routine in Figure 8, and the microinstruction ``''EN'' can be executed in the last microstep.
At the same time, before each of tests 1 to n of the operation confirmation test program shown in Figure 7, a ``start CPU command'' is added to point to the start address of this independent test initialization routine. Just add it.

The general register save/restore routines may also be made independent in the same way.

(Details are shown in Figure 9 and will be discussed later) Next, a second modification will be described.

In this embodiment, for the purpose of simplifying the hardware, the existing one-instruction mode is used to detect the end of a specified microstep sequence and stop the CPU.

However, depending on the microprogram of the information processing device to which the present invention is applied, it may be difficult to use the microstep sequence in this manner, and it may be difficult to use the microstep sequence in this manner or only by executing a single microstep. Sometimes it is difficult to design.

In such a case, "CP from specified microstep"
It would be convenient to have a command that starts J and stops the CPU after executing a specified number of steps.

The number of steps specified here is usually 2-3 steps to 5.
Since the number of steps is up to 6 steps, the command format shown in FIG. 5 may be changed to include a count field of approximately 3 bits.

It is easy to install a counter in a dedicated control circuit and send a stop signal to the CPU after the CPU has executed a specified number of steps.

Next, a third modification will be described.

In this embodiment, there is a DIS instruction that corresponds to the state where the CPU is waiting for an input/output interrupt, and it is easy to detect whether the CPU is waiting for an input/output interrupt, but there is no such special instruction, and the program loop There are also information processing devices that create a system to wait for an interrupt to occur.

In that case, you can change the hardware and system software so that the hardware can know that the CPU is waiting for an input/output interrupt by creating a new instruction code or using unused bits in the instruction word. change.

Changes will vary depending on the individual device.

Next, a fourth modification will be described.

In this modified example, a failure in which the flip-flop FZ is always "1" cannot be detected.

After step Sd in FIG. 4, if a test is inserted to confirm that the flip-flop FZ is reset before restoring the general register, the failure detection rate will be increased.

Above, an example of applying the present invention in its simplest form has been described.

In many cases, sufficiently good results can be obtained even with the simplest application example described above, but the points required for failure detection and their importance differ depending on the application case.

In order to better meet such wide-ranging requirements, it is recommended to incorporate one or a combination of the following variations.

Other embodiments will be described in detail below.

In the above embodiment, the operation confirmation test is executed when the CPU is in an idle state waiting for input/output, so the time from the occurrence of a failure to the detection of the failure is usually sufficiently short. However, there is no fixed upper limit.

Depending on the information processing system, for example, the information processing capacity may be 0.
．． It doesn't matter if it drops by 1 width, so make sure to test it for 1 second (I want to test the operation at least once).

There are demands like this.

An example in which it is necessary to set a lower limit on the frequency of execution of such an operation check test will be described below.

A flowchart of the DIS command and operation confirmation test of the embodiment is shown in FIG. 9, and since the hardware changes are small, they are not shown.

A counter RTT is newly installed in the dedicated control circuit, and the RTT
A count pulse for the timer in the CPU is added to.

In the case of the above system, the bit length of the RTT is selected so that it will overflow when the timer count pulse continues to be applied for one second.

The RTT overflow signal is sent to the sequence control section.

If the sequence control unit has the rXIPfi number,
When the microinstruction ``END'' is issued, instead of sending the address of the starting address of the microprogram of the next instruction to the control storage device, the address of the starting address of the interrupt processing routine is sent.

” logic, so we can extend its functionality and add a microinstruction “if there is an RTT overflow signal”
Adds a function to send the address St to the control storage device when "END" is issued.

Here, St is shown in FIG.

FIG. 9 shows an embodiment in which the above-described modification 1 and the lower limit setting of the execution frequency of this operation confirmation test are added to the above-described embodiment, and D
A flowchart of an IS instruction microprogram and operation confirmation test is shown.

As shown in the DIS instruction flowchart for this embodiment, St is the starting address of the routine that starts the operation confirmation test.

The differences from the test programs shown in FIGS. 4 and 7 will be mainly explained below.

In addition to the conventional execution of the DIS instruction, the entry point of the microprogram flowchart for the DIS instruction is as described above. There is a method in which the sequence control section executes a routine starting from step St.

The loop that waits for the microinstruction ``END'' is executed by the hardware of the sequence control unit as described above, and does not actually exist as a microstep, so it is shown by a broken line in FIG.

The test initialization routine that was executed after saving the general register is made into an independent routine (not shown) according to modification 1, and its starting address is St.

Therefore, the saving of the general register is immediately followed by the step of issuing the microinstruction "start test", and the "start CPU, SI command" is issued prior to each test in the operation confirmation test.

The structure of the operation confirmation test can be simplified by considering the initialization, the test, and the accumulation of test results as a test block before each test in the operation confirmation test.

After the operation confirmation test is completed and the general register and indicator are restored, the counter RTT is cleared to zero.

This means that the elapsed time after execution of the operation confirmation test is measured by RTT.

After the operation confirmation test is completed, an input/output wait state occurs within a certain period of time, and if the operation confirmation test is executed, the RTT becomes zero again at that point.

In this way, when the input/output wait state occurs more than once within a certain period of time, the operation can be tested without consuming the information processing capacity that should be available to the user, just as in the simplest embodiment described above. executed.

Only when an input/output wait state does not occur even once within a certain period of time, RTT overflow occurs, and an operation confirmation test is performed while waiting for processing of the next instruction to be executed.

As a result of executing the DIS instruction, if an operation check test is performed, FDIS is set, so after clearing the RTT to zero as described above, the program enters a loop waiting for an input/output interrupt.

Furthermore, when the operation confirmation test is executed as a result of RTT overflow, the FDIS has been reset, so after clearing the RTT to zero, processing of the next instruction is immediately resumed without waiting for an input/output interrupt.

In the case of the embodiment of the present invention, the control-related registers (registers that are invisible to the software) have been damaged due to the operation confirmation test, so the microinstruction "EN" has been destroyed.
Before issuing "D" and starting processing of the next instruction, a routine for restoring those registers is executed, which is shown in FIG. 9 as preparation for restarting instruction word processing.

Furthermore, when entering from the DIS instruction, execution of the next instruction after the DIS instruction does not begin immediately and the process always goes to the interrupt processing routine, so there is no need to execute this instruction word resume preparation routine.

The transfer of control between the DIS instruction microprogram and the operation confirmation test program is indicated by dotted arrows in FIG. 9, although this is a minor detail.

In the case of the DNS instruction, it is an instruction that is executed only in master mode, so it was not a problem in the explanation so far, but the distinction between master and slave can also be used as part of the general register or indicator in the operation confirmation test. You have to evacuate and return before and after.

This is because if you do this, you may have to enter an operation confirmation test from slave mode.

For this reason, the registers representing master/slave are designed separately from the mode register for setting the l-instruction mode.

Next, as yet another embodiment, a case where a short interrupt response time is required will be described.

In the simplest embodiment shown in FIG. 4, when the DIS instruction is entered, an operation confirmation test is first performed, and then a loop waiting for an interrupt is entered.

Therefore, if an interrupt request occurs immediately after entering the DIS instruction, the interrupt request will be served for the time necessary to execute the operation check test, and as a result, the information processing capacity that can be used by the user will be reduced. This means that the operation check test is performed by consuming a lot of time, and the response to the interrupt becomes longer by the time required to execute the operation check test.

Regarding the former drawback, a new timer like the one mentioned above was installed for the purpose of setting an upper limit on the execution frequency of the operation check test, and each time the operation check test was executed, the timer was cleared to zero, and a newly installed test control flip-flop was also set. When the timer overflows, the test is prohibited while the test flip-flop is set (one of the branch conditions in the flowchart in Figure 4), and operation confirmation tests are executed unnecessarily frequently. I will make sure that it does not happen.

It can be improved considerably by this method.

However, such a method does not eliminate the latter drawback, but only has the effect of reducing the probability that the latter drawback will actually occur.

Hereinafter, a modified example will be described in which the operation check test is interrupted immediately when an input/output interrupt request occurs so that the response time to the interrupt request does not become long due to the operation check test.

As mentioned above, according to the investigation of the CPU according to the embodiment of the present invention, idle states occurred with sufficient frequency even if only idle states that lasted for 1 millisecond or more were investigated.

In other words, this indicates that the operation confirmation test may be interrupted when the idle state ends in a short period of time.

First, the XIP signal is also sent to the dedicated control circuit, and when the XIP signal comes during execution of the operation confirmation test, the command is read from a specific address in the dedicated memory, regardless of the address of the dedicated memory read last.

The command is almost the same as the last four words of the operation confirmation test program in Figure 7, which returns the mode register to the normal mode and reads the CP from a specific address (Sr address) in the control memory.
It is sufficient to start U and then put the dedicated control circuit in a standby state.

In a microprogram starting from a specific address Sr, it is sufficient to return to the general register, reset the FDIS, and then proceed to the interrupt processing routine.

That is, in the example of FIG. 4, the starting address of the general register return routine may be set to Sr.

However, when making this change to FIG. 9, in the microprogram starting from address Sr, after restoring the general register, the counter RTT is left as it is without being cleared to zero, and the interrupt wait loop or instruction word processing is performed. It is necessary to go to the restart preparation routine.

(When starting the CPU from address Sr, the operation confirmation test had not yet been completed, so it was not possible to determine whether there was a failure or not.

) An embodiment incorporating the above changes along with other changes will be described later.

Next, an embodiment in which an operation confirmation test can be started from software will be described in detail.

The fault detection method of the present invention (as described above, the fault detection is performed in a sufficiently short time of, for example, 1 second), so it can be used not only in batch processing systems but also in most online data processing systems. It has sufficient ability to be used as a main failure detection means.

However, in some online data processing systems, once incorrect information caused by a malfunction is passed to a terminal device, for example, in a case where there is a problem with an unspecified number of people, the system malfunctions immediately after that. Even if erroneous information is detected, it is difficult to cancel the effects of that erroneous information.

Even in that case, such important information that is difficult to redo is only issued once per transaction.
For example, in many cases, the information processing apparatus can perform processing up to about 10 times per second.

When the program reaches such an important point, the program starts an operation check test to confirm that the information processing device is working properly, and then sends such important information to the terminal. Even if there is, the scope of redoing is limited, which is convenient.

Furthermore, even if the system queries and updates the database and has a checkpoint file, a transaction file for recovery, etc. so that it can be restarted in the event of a failure, for example, before creating the checkpoint file, If a program can first start an operation check test to confirm the correctness of the information processing device, it will be possible to easily clarify recovery procedures when a failure is discovered.

In such a case, it is easy to insert a new instruction code or add a variation of an existing instruction to the flowchart shown in FIG. 4 by specifying a software instruction.

However, in this case, if the test is prohibited, it is better to proceed to the exception handling routine as an abnormal situation, rather than just ending the process as shown in FIGS. 4 and 9.

Also, after restoring the general register, for example, FDIS
It is necessary to determine that the operation confirmation test started from the software has ended by checking the , etc., and move on to processing the next instruction without entering an input/output waiting loop.

An embodiment incorporating this change along with other changes will now be described.

First, we set a lower limit on the execution frequency of the operation check test, and improved the implementation so that the operation check test does not increase the response time to an interrupt request, and so that the execution of the operation check test can be started by a software command. An example is shown in FIG.

The embodiment will be described below, focusing on the differences between FIG. 10 and FIG. 9 and the points not shown.

In this embodiment, a new command ``TEST'' is added to start an operation confirmation test by utilizing a vacant space in the conventional instruction code.

When this instruction is executed, the FrEST flip-flop is first set.

The function of the FTEST flip-flop will be described later.

Next, check whether the test is prohibited or not. If the test is prohibited due to some reason such as a parity error in the dedicated memory, the work expected from the software will not be completed. Since this is not possible, we move on to the exception handling routine.

Normally, after saving general registers, indicators, master/slave mode distinction, etc., an operation confirmation test is started.

The operation confirmation test is performed using the dedicated memory 774(8)-7 as shown in FIG. 10 as an operation confirmation test program.
The process is the same as that shown in FIG. 9 except that a post-processing command string as shown in FIG. 10 is added to address 77(8).

The dedicated control circuit was slightly modified, and during the operation confirmation test,
A function has been added to forcibly set 774 (8) in the address register of dedicated memory when an IP signal is sent.
Using this function, execution of the operation confirmation test is interrupted.

Also, when FTEST is set, this function does not work, so that all operation confirmation tests started from the software are always performed.

If an operation confirmation test is started due to waiting for an input/output interrupt or timer RTT overflows, and the XIP signal becomes 1 while the test is being executed, the next command is 7 7 4 (8 ) address, and as a result, the CP immediately returns to normal mode.
Return U and start executing the microprogram from Sr.

The microprogram starting from Sr can do exactly the same job as the general register restoration routine described in the previous embodiments.

In Figure 10, the same routines are written to coexist for simplicity, but in reality, the general register restoration routine is called by a subroutine call at the microprogram level, so the routine starting from Sr takes only l steps. It's done.

When the restoration of the general register is completed, the process immediately proceeds to the step of testing FDIS without clearing the counter RTT to zero.

Considering the case where the operation confirmation test started by the overflow of timer RRT is interrupted by an input/output interrupt, after the general register is restored, preparations are made to resume instruction word processing and the microinstruction ``END'' is executed. At this point, the sequence control section moves to the interrupt processing routine.

Also, this microstep that issues "END" is executed even if the operation confirmation test started by the test command confirms that there are no failures and ends normally, so FTEST
We are also working on resetting the system.

As described above, according to the present invention, since the bit length of the dedicated memory is small, a low-cost detection method can be implemented, and since the inspection is at the microinstruction level, minute inspections can be performed efficiently.

Furthermore, the time required from the occurrence of a failure to the detection of the failure is sufficiently short, and the information processing capacity available to the user is hardly consumed.

Furthermore, since the test items are stored in a dedicated memory, application of the present invention does not affect the content (software) stored in the main memory, making it suitable for information processing equipment that uses a microprogram method or for hard-wired control. The present invention can be widely applied even when the present invention includes parts, and can also be easily applied to failure detection in control circuits and arithmetic circuits in which parity checks are difficult.

[Brief explanation of the drawing]

Fig. 1 is a schematic diagram of a central processing unit that uses a microprogram system, Fig. 2 is an operational concept and DIS command flowchart of the microprogram, Fig. 3 is a diagram of the hardware configuration of the information processing device of the present invention, and Fig. 4 5 is a flowchart of the execution of the DIS command in the information processing apparatus of the present invention, FIG. 5 is a format of commands used in the present invention, and FIG. 6 is a table showing the types of commands used in the present invention. Further, FIG. T shows an example of the contents of the operation confirmation test program in the dedicated memory used in the present invention, FIG. 7A shows a modification of the test program in FIG. 7, and FIG. Test result accumulation routine example, Part 8-
FIG. A shows a modification of the test result accumulation routine of FIG. 8 and the determination steps. FIG. 9 is another embodiment of the present invention, and shows a flowchart of the DIS command and an operation check test program in which a lower limit of the execution frequency of the operation check test is set. Fig. 10 shows still another embodiment, which is a flowchart of the DIS command and an operation confirmation test program. DESCRIPTION OF SYMBOLS 1... Control storage device, 2... Sequence control unit, 3... Micro instruction register, 4...
. . . Arithmetic unit, 5 . . . General register GR. 6...Scratch pad memory SPM,
7... Working register RT, 8...
・Operand register RD, 9.10...Selector, 11...Logic operation unit ALIJ, 1 2
... Indicator, 20 ... Operation confirmation test circuit, 21 ... Dedicated memory, 22 ...
...Address register, 23...Selector, 24...Command register, 25...
・Data register, 26...Data path, 27
... Dedicated control circuit, 2B ... External device interface.

Claims (1)

[Claims] 1. Control storage device storing a microprogram;
a central processing unit having a microinstruction register and an arithmetic unit for storing microinstructions read out from the control storage device; a storage device; (2) means that is activated when the central processing unit becomes idle and reads commands from the dedicated storage device;
The dedicated control circuit includes a means for interpreting and executing the command, and the dedicated control circuit activated when the central processing unit becomes idle executes the command according to the command read from the dedicated storage device. Information characterized in that the control storage device is addressed, and the central processing unit performs an operation confirmation test of the arithmetic unit by executing a microstep or a microstep sequence read from the control storage device according to the command. Processing equipment. 2. In the information processing device described in claim 1,
An information processing device characterized in that the dedicated storage device stores an address for a control storage device as a command in order to read out microinstructions necessary for performing an operation confirmation test. 3. In the information processing device according to claim 1, is it possible to perform an operation check test on the DIS instruction that has the function of keeping the central processing unit in an idle state until an external signal is given? An information processing device characterized by having a microstep for determining whether or not to do so. 4 In the information processing device according to claim 3, when the central processing unit becomes idle and becomes capable of executing an operation confirmation test, the central processing unit stores the data stored in the internal general register. Preparing for the operation check test by executing microsteps for saving to the device, microsteps for the initialization routine for the operation check test, and microsteps for activating the dedicated control circuit in the operation check test circuit that is in standby mode. An information processing device characterized by: 5. In the information processing device according to claim 1, the dedicated control circuit activated at the start of the operation confirmation test reads out commands stored in the dedicated storage device, and uses the read commands to read out the commands stored in the control storage device. An information processing device characterized by addressing the device. 6. In the information processing device according to claim 1, the dedicated control circuit starts the read operation of commands stored in the dedicated storage device, and performs information processing to enable the central processing unit to operate in a single instruction mode. Device. 7. In the information processing device according to claim 1, when a command for a test operation is read from the dedicated storage device, the dedicated control circuit addresses the control storage device with the command and writes the microprogram. An information processing device characterized by executing a test operation at a level. 8. In the device according to claim 1, the microstep sequence of the test result accumulation routine collects the processing results stored in various registers in the central processing unit by testing at the microprogram level and compresses them into a compressed data amount. An information processing device, characterized in that the following is stored in a control storage device. 9. The information processing device according to claim 1, characterized in that the test results of all test operations are obtained as compressed data obtained during processing of the test result accumulation routine of the final test operation. Information processing device. 10 In the information processing apparatus according to claim 9, after the operation confirmation test is completed, the data is
An information processing device characterized in that a command for restarting an IS instruction is read out, a control storage device is addressed by the command, and the central processing unit is restarted for the DIS instruction. 11. The information processing apparatus according to claim 1, wherein the dedicated control circuit executes any microstep or step sequence specified by the command, waits for the completion of the execution, and then executes the next command. An information processing device characterized by reading data from a dedicated storage device. 12. The information processing apparatus according to claim 1, further comprising a timer that measures the elapsed time after execution of the operation confirmation procedure, and when the information processing section enters an idle state and the timer An information processing apparatus characterized in that the information processing apparatus is activated to execute the operation confirmation procedure when the time measured by the information processing apparatus exceeds a certain value. 13. The information processing apparatus according to claim 1, wherein the dedicated control circuit suspends execution of an operation confirmation procedure in response to termination of the idle state. Processing equipment. 14. The information processing apparatus according to claim 1, wherein the dedicated control circuit is activated when a specific instruction is executed and when the information processing section enters an idle state; An information processing device characterized in that a procedure for confirming the operation of the information processing section is executed by reading a command from a dedicated storage device and executing an arbitrary microstep or a series of microsteps in the control storage device.