JPS5837991B2 - Manufacturing method of semiconductor device - Google Patents

Description

[Detailed description of the invention] The present invention relates to a method of manufacturing a semiconductor device.

In the manufacture of semiconductor devices, a part of the insulating or protective field oxide film provided to cover the electrodes and wiring parts of the semiconductor device is penetrated and removed to connect the diffusion regions and electrode regions to external electrodes. It is necessary to provide a contact hole for this purpose.

Further, the wall surface of this contact hole is generally tapered to facilitate and improve subsequent connection.

In order to create this taper, the field oxide film has been constructed of two or more layers of oxide films having different etching rates.

One of the structural methods is, for example, etching the surface layer of the field oxide film with phosphosilicate glass (which has a high etching rate) at a high concentration.
(hereinafter abbreviated as PSG) layer, and the lower layer is a layer with a low concentration and a low etching rate.

Conventional methods for forming this surface layer PSG film include the vapor deposition method (a method of forming a film of the material to be deposited on the surface of the material to be processed by a reaction on the surface of the material to be processed in the vapor phase).

) and methods using phosphorus diffusion at high temperatures were used.

Contact holes and tapers are formed using the PSG layer obtained in this way, but in the above method, the PSG layer is
It is difficult to obtain a PSG layer that always has a constant surface concentration and thickness because variations in the G film thickness and variations in the phosphorus concentration of the PSG film tend to occur within the wafer, within the manufacturing loft, and between lofts.

Furthermore, due to variations in the surface concentration of the PSG layer, stable and good contact holes and their tapers obtained by utilizing this surface concentration could not be obtained.

SUMMARY OF THE INVENTION An object of the present invention is to provide a manufacturing method that eliminates the above-mentioned drawbacks and always provides a stable and constant contact hole and taper.

The details of the present invention will be explained below with reference to Examples.

The figure is a cross-sectional view showing the state of a semiconductor device during the manufacturing process of an insulated gate field effect transistor.

In the present invention, as shown in FIG. 1, an insulating and protective film is applied to the entire surface of the wafer 1, on which the source S and drain D regions and the gate G electrode via the gate insulating film 10 have been formed, by a vapor phase method or the like. A polycrystalline Si layer 3 is formed on the field oxide film 2 formed by a vapor phase growth method using, for example, a mixed gas of monosilane (SiH4) and N2 or Ar.

Next, phosphorus is diffused into the field oxide film through this polycrystalline Si layer while keeping the wafer in this state at a high temperature.

This phosphorus diffusion can be performed, for example, by placing a glass layer 4 containing phosphorus, such as glass containing P205, on the polycrystalline Si layer and placing it in a high-temperature atmosphere of N2 or 02 at the same time or afterward, as shown in FIG. Can be done.

At this time, phosphorus passes through the polycrystalline Si and reaches the field oxide film, where the concentration decreases from the surface to the inside of the PSG film.
Layer 5 is formed (FIG. 2).

The concentration and concentration gradient formed are controlled by the thickness of the polycrystalline silicon layer and the conditions for phosphorus diffusion.

Next, the glass layer 4 containing phosphorus and the polycrystalline Si layer 3 are removed (FIG. 3).

Here, the contact hole is patterned using PEP technology (photo-etching), and the field oxide film is etched using the resist as a mask to form the contact hole 6 (FIG. 4).

In the diffusion of phosphorus into the Finored oxide film, the phosphorus supply source is not a phosphorus-containing glass layer formed on polycrystalline silicon, but phosphorus-doped polycrystalline silicon is formed on the field oxide film, and the following is the same as above. A desired PSG layer can also be formed by placing it in a high temperature atmosphere.

The present invention is as described above, and according to this method, (1) a PSG layer with a predetermined concentration can be easily obtained by controlling the thickness of the polycrystalline silicon layer 2 and the conditions for phosphorus diffusion; .

(II) Since the glass layer containing phosphorus is not directly attached to the field oxide film but on the polycrystalline silicon layer, sufficient etching can be performed when removing the phosphoric acid glass, so there is no risk of the glass layer containing phosphorus remaining. Moreover, there is no fear that the PSG layer will decrease.

Furthermore, even if there is a defect in the field oxide film, there is less risk of the defect being magnified.

(I) Even when the polycrystalline silicon layer is removed, since the phosphorous-doped polycrystalline silicon layer has a fast etching rate, the reduction of the PSG layer under the polycrystalline silicon layer can be minimized.

(IV) Since the surface concentration of the PSG layer on the surface of the field oxide film is stabilized, variations in the taper of the contact hole are reduced and stabilized.

The following effects can be obtained.

[Brief explanation of drawings]

1 to 4 are cross-sectional views of essential parts of a wafer in each step of an embodiment of the present invention. 6... Contact hole, 2... Field oxide film, 3... Polycrystalline silicon layer, 4... Additional type layer containing phosphorus.

Claims (1)

[Claims] 1. Phosphorus doped into a polycrystalline silicon layer formed to a predetermined thickness on a field oxide film that has already been formed prior to the contact hole formation process in the manufacture of semiconductor devices, or an impurity that is not doped. After diffusing the phosphorus contained in the additionally formed layers on the polycrystalline silicon layer through the polycrystalline silicon layer and controlling the impurity concentration and concentration gradient in the depth direction, the additionally formed layers are removed. A method for manufacturing a semiconductor device, comprising the step of forming a contact hole having a stable taper using the field oxide film having the phosphorus diffusion concentration and gradient thus formed.