JPS5838813B2 - logical device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a logic device, and more particularly to a logic device equipped with a delay time monitoring circuit.

FIG. 1 shows a normal logic circuit.

The outputs of a group of latches are input to a combinational circuit, and the outputs of the combinational circuit are again supplied to some latches and stored.

At this time, part or all of the latches on the output side may be the same as the latches on the input side.

Faults that occur in such logic circuits include not only faults in the circuit elements themselves but also faults due to excess delay time of the circuit elements.

This is because the clock is applied to the output latch group in Figure 1,
This occurs when the logic operation in the combinational circuit is not completed at the time the output latch group is set.

This delay time excess occurs due to various factors such as an increase in delay time due to element deterioration and a logic design error.

Among logical device failures, malfunctions caused by the delay time exceedance are one of the most difficult to identify.

An object of the present invention is to generate a warning signal when the delay time of a logic device exceeds a predetermined tolerance, thereby facilitating the investigation of the cause of a malfunction. A normal operation latch L1 operated by a normal clock, a monitoring latch L2 in which at least one of a signal input and a clock has a different time relationship from the normal signal input and the normal clock, and an output of the normal operation latch L1. and a comparison circuit for comparing the output of the monitoring latch L2, and the operating state of the normal operation latch is monitored based on the output of the comparison circuit.

Hereinafter, the present invention will be explained with reference to the drawings.

FIG. 2a is an embodiment of a circuit providing a delay time monitoring function according to the present invention, and is a time chart of the circuit of FIG. 2a.

In FIG. 2a, Ll, L2. L3 is latch, DLY
is a delay circuit, G1 is an exclusive OR (FOR)
The gate and CLOCKi are clocks, among which latch L1 is a latch used in the normal system, and latches L2 and L
3. The delay circuit DLY and the exclusive OR (EOR) gate G1 are circuits for monitoring delay time.

As DLY, the wiring length may be simply increased, or gates such as AND and OR may be inserted.

Other generally known methods may also be used.

In a device that guarantees that the normal latch L1 operates with a margin of Mns or more during normal operation, the DLY delay value is set to Mns.

(This value does not need to be controlled very tightly.

) The input signal A of the latch L1 is Mns.
While the input signal B of the latch L2 reaches the clock with a margin above, the input signal B of the latch L2 can also be in time with the clock, and the output X of the latch L1
and the output Y of latch L2 are always equal, and the output of G1 is O”
It is.

Therefore, the output Z of L3 becomes "O", indicating that the delay time has not been exceeded (meaning that the allowable margin has been exceeded).

When the signal A no longer has a margin of more than Mns, a state occurs in which the signal reaches the latch L1 but not the latch L2, and X and Y become inconsistent.

At this time, the output of G1 becomes "1" and latch L3 is set to generate a warning signal.

In FIG. 2a, DLY is inserted only in the data input section of the latch, but it is also possible to monitor the delay time excess of the clock enable signal of the latch.

In this case, DLY may be similarly inserted into the clock enable signal of latch L2.

FIG. 3a is a time chart of the circuit of FIG. 3a in another implementation for monitoring delay time.

The explanation of each circuit is the same as that in FIG. 2a. The circuit of FIG. 3a differs in that instead of inserting DLY into the input of latch L2, the clock phases of latches L2 and L3 are advanced by Mns than the clock phase of latch L1.

If you do this, the signal that reaches latch L1 will be sent to latch L.
As long as there is a margin of Mns or more with respect to the clock of 01, the same signal is set in the latch L2, so no mismatch will be detected by 01.

(The period from when a clock is applied to latch L1 to when the next clock is applied to latch L2 is defined as an effective comparison period.

) If the input signal to latch L1 no longer has a margin of more than Mns, a correct input signal will be set to latch L1 and an incorrect signal will be set to latch L2.

At this time, G1 detects a mismatch between latch L1 and latch L2, and latch L3 is set to generate a warning signal.

In addition, as a circuit that combines the circuits shown in FIG. 2a and FIG. 3a, although not shown, the circuit shown in FIG.
A circuit in which the delay circuit DLY shown in FIG. 1 is inserted may be considered.

In this case, if the delay value Dnss of DLY is made to emit the clock of latch L2 by a time Cns earlier than the clock of latch L1, the time when the input signal of latch L1 arrives with no margin of more than (C+D) ns. In this case, the input signal is correctly set in the latch L1, and the incorrect signal is set in the latch L2.

At this time, G1 detects a mismatch between latch L1 and latch L2, and latch L3 is set to generate a warning signal.

Next, FIG. 4a is a circuit of still another embodiment of the present invention, which is a time chart of the circuit of FIG. 4a.

FIG. 4a is completely the same as FIG. 3a in terms of circuit configuration.

However, the clock of latch L2 is slightly delayed from the clock of latch L1, and the clock of latch L3 is in phase with the clock of latch L1.

If this is done, the output of the latch L3 will indicate that the input signal of the latch L1 has exceeded the delay time and has not been correctly set in the latch L1, that is, a malfunction has occurred.

This is because if the input signal of latch L1 exceeds the delay time, latch L1 will not be set correctly, but latch L1
It is now possible to set the latch L2, which has a slower clock, and the output of the latch L1 and the output of the latch L2 will show a mismatch (more precisely, in the period from the clock of the latch L2 to the clock of the next latch L1). It is.

Therefore, the output of the latch L3 in FIG. 4a is not a warning signal but a failure detection signal, and has a slightly different meaning from that in the cases of FIGS. 2a and 3a (warning signal).

The output of latch L3 of FIGS. 2a and 3a is a delay warning signal indicating that the delay time no longer satisfies a given margin, which can be used as follows.

■ One of the machine check interrupts to report to the program.
Cause.

■ Stop the device.

■ Place the device in checkstop (clock stop) state.

■ Use this as an opportunity to switch the clock cycle (to a slower one).

(Hardware Switching) It is also an effective method to be able to set which of the above functions (1) to (2) to select (or completely ignore) using some means.

As a result of the above (■), the following becomes possible.

(a) Logging of information regarding areas where the delay time does not have a predetermined margin and preventive maintenance based on this information.

(b) Switching machine cycles under software control to ensure normal operation of the device.

A possible method for instructing the hardware to switch machine cycles is, for example, issuing a diagnostic command.

As described above, according to the present invention, the delay time of a logic device can be monitored, and a delay warning signal or a failure detection signal based on the delay can be output, so that the reliability of the logic device can be improved. be effective.

[Brief explanation of drawings]

FIG. 1 shows a conventional logic circuit, FIGS. 2, a to 4 a, respectively, circuits of different embodiments of the present invention, and FIGS. 2 b to 4, respectively, to FIG. 2. 4 is a time chart of the circuit of FIG. 4a. In the figure, L1 to L3 are latches, G1 is an exclusive OR gate,
CLOCKl and CLOCK2 are clock and DL, respectively.
Y is a delay circuit.

Claims (1)

[Scope of Claims] 1. A latch L1 for normal operation operated by a normal signal input and a normal clock, and a monitoring device in which at least one of the signal input and the clock has a different time relationship from the normal signal input and the normal clock, respectively. a comparison circuit for comparing the output of the normal operation latch L1 and the monitoring latch L2, and monitors the operating state of the normal operation latch based on the output of the comparison circuit. A logical device characterized by the following. 2. To the monitoring latch L2, the normal signal input or its copy signal is delayed by a time M and is given as an input signal, and a clock that is in phase with the normal clock is given as a clock, and the normal operation latch L1 outputs. Claim 1 is characterized in that it is detected that the system of the normal operation latch L1 no longer has a margin of time M due to a mismatch between the output of the monitoring latch L2 and the output of the monitoring latch L2. Logical device described. 3. Input the regular signal input or its copy signal to the monitoring latch L2 at a time equal to the arrival time of the input signal to the regular operation latch L1, and generate the clock a time M earlier than the regular clock. and the output of the normal operation latch L1 and the output of the monitoring latch L2 did not match between the generation of the normal clock and the generation of the clock of the monitoring latch L2. 2. The logic device according to claim 1, wherein the logic device detects that the system of the normal operation latch L1 no longer has a margin of time M. 4. To the monitoring latch L2, the above normal signal input or its copy signal is delayed by a certain amount of time and is given as an input signal, and a clock that occurs earlier than the above normal clock by a time C is given as a clock, so that the above normal operation is performed. Since the output of the latch L1 and the output of the monitoring latch L2 do not match after the normal clock generation until the next clock generation of the monitoring latch L2, the system of the normal operation latch L1 is 2. The logic device according to claim 1, wherein the logic device detects that the time (D+C) is no longer available. 5. Input the regular signal input or its copy signal to the monitoring latch L2 at a time equal to the arrival time of the input signal to the regular operation latch, and provide a clock that occurs later than the regular clock. , the output of the normal operation latch L1 and the monitoring latch L2.
Detecting that the normal operation latch L1 has not been able to correctly receive the input signal because the output of the monitor latch L2 is not at the same level from the time when the clock is issued to the time when the normal clock is issued. The logic device according to claim 1, characterized in that: