JPS5839337B2 - Reciprocal calculation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an arithmetic circuit for a digitally controlled automatic exposure camera, and more particularly to a reciprocal calculation circuit for displaying the reciprocal of a shutter time.

In general, the shutter time T provides information on the amount of light, and when film sensitivity information ASA and aperture information are F, the relationship between them is given by the following equation.

K is a constant.

T=K・(1/L)・(1/ASA)・F In other words, information on the reciprocal of the light amount (1/L) and the reciprocal value of the film sensitivity ASA (
1/ASA) and aperture information F (F=A2 when the F number is A), an appropriate shutter time can be obtained.

Conventionally, analog circuits have been used to calculate this shutter time.

However, since the information ratio of the amount of light covers a wide range of 10 to the 6th power or more, a configuration is used in which each amount of information is logarithmically compressed, multiplication is replaced with addition, and the result is logarithmically expanded.

However, this circuit is difficult to adjust and requires strict requirements regarding accuracy and variation in component characteristics.

If the circuit is constructed using an analog method, the number of parts can be relatively small, but errors due to voltage fluctuations and temperature changes tend to be quite large.

On the other hand, digital methods have the great advantage of being able to control with high precision without imposing strict requirements on semiconductor components, making adjustments much easier, and making digital display easier, but on the other hand, the circuits become more complex and the number of parts increases. However, it is disadvantageous in terms of space, and it is difficult to keep the photometry time and calculation time within the desired short time, resulting in a lack of quick shooting performance, which may be a decisive drawback for the camera.

However, it is certain that these drawbacks will be overcome by the adoption of high-density integrated circuits (LSI), and the great advantages of digital technology will be utilized, and that the digitalization of camera control circuits will progress even further than at present.

When calculating the shutter time, the unit is usually calculated in the form of [time] for convenience of automatic exposure control.

However, when expressing the shutter exposure time, as is well known, if it exceeds 1 second, it is 2 seconds, 4 seconds, 8 seconds, etc.
The shutter scale is displayed in units of [time] like this, but if the shutter exposure time is 1 second or less, the shutter scale is 1.2.4.8.15.・・・
・・・・・・・・・・・・・・・500.1000゜・・・
The unit is displayed as the reciprocal of [speed], and for example, 1 millisecond is displayed as 1000.

Therefore, if the digital display in the digital control circuit is to follow the conventional shutter exposure time display method, it is possible to display a period of 1 second or more using a completely known method, since the calculation result can be displayed as is.
Displaying seconds or less requires some kind of conversion processing.

The present invention was made by focusing on the problem of calculating the reciprocal of the shutter time.

As is well known, when performing division, two registers, an operation register and an operand register, and B, C, and D (
(Binary Coded Decimal) A method is used in which a subtraction circuit is used to repeatedly subtract the contents of the operation register from the contents of the operand register, and the number of subtractions executed until the result of the subtraction becomes zero is the quotient.

A schematic circuit configuration for implementing this method is shown in FIG.

In FIG. 1, the contents of shift registers 1 and 2 enter input a of subtractor circuit 90, and shift register 4 enters input a.
The result a-1) is returned to shift registers 1 and 2 again.

1 is added to the shift register 3 every time a subtraction is performed.

Shift register 1 is used to detect excessive subtraction, and 6 correction is not performed for this digit.

Every time it is detected that the digit has been subtracted too much, the contents of the dividend register 2 are returned to the previous state by one, the digit is shifted to the left, and the subtraction is continued.

Therefore, register 3 stores the quotient.

The shift register 5 is a boundary register, and the subtraction stop detection circuit 10 detects that the most significant digit of the quotient has reached this digit, and then the subtraction ends when a borrow occurs in the shift register 1.

The shift register 7.8 is used to match the number of digits of the operand registers 1, 2.3 and the operation register 4.5.6.

Although this method provides accurate results, at least two shift registers are required for the operation.

Considering that multiplication is performed in calculating the shutter time, an addition circuit is always used, so a switching circuit is required to perform subtraction operation, and the calculation time becomes longer at the cost of obtaining accurate results. .

Let us consider a case where such a circuit is used to realize a back calculation circuit for displaying camera shutter speed.

Assuming that the calculation result is calculated to three digits in order to obtain sufficient precision, the quotient will take a maximum of 999, so at least 3X 10
= 30 word times of calculation time are required.

On the other hand, as a requirement for camera operation, photometry, shutter time calculation, and time until reciprocal display (shutter time) must be completed within a certain allowable time.

This fixed period of time is spent from when you start pressing the shutter button until the shutter mechanism starts operating, or to be more precise, after the light metering start switch is turned on, the shutter mechanism starts operating according to the shutter calculation result. Assuming that the time required to complete the calculation is approximately 20 m5, and if a maximum of 30 word times are required just for the reciprocal calculation, this becomes virtually impossible.

On the other hand, if you allow enough time for the calculation,
Immediate response, which is the basic performance of the camera, would be impaired, or the circuit itself would become expensive.

The present invention has been made in order to solve the above-mentioned problems in digital calculations, and an object of the present invention is to provide a reciprocal calculation method that can perform reciprocal calculation for display within a short period of time while maintaining necessary and sufficient accuracy. The purpose is to provide circuits.

To achieve this objective, the reciprocal calculation circuit according to the present invention is configured to include one shift register, a BCD addition circuit, and a simple control circuit, taking advantage of the fact that the number of digits for display is only two. It is.

The shift register and the adder circuit repeat the 2x operation and the 1.1x operation to calculate a necessary and sufficient reciprocal number.

According to such a configuration, the object of the present invention is completely achieved.

The present invention will be explained in more detail below with reference to the drawings showing embodiments.

FIG. 2 shows an arithmetic circuit that calculates a reciprocal using one shift register.

This figure shows the configuration circuit for obtaining the calculation result up to three digits and rounding down the fourth or lower digits.

That is, the divisor is rounded to three significant digits and stored one by one in shift registers 12, 13, and 14 starting from the most significant digit, and O is placed in shift register 11.

The quotient will be stored in shift registers 15, 16, 17, and 18, and before the start of calculation, X3-
1 Enter x, -x2=x4=0.

Gates 19, 20, 21, and 22 constitute a switching circuit,
A reciprocal calculation pulse is input to the input terminal 33, and while the reciprocal calculation pulse is at a high level, an operation is performed, and while the reciprocal calculation pulse is at a low level, the contents are held.

The shift register 38 has gates 26, 27, 28, and 29 corresponding to one digit length for the 2x operation and the 1.
It constitutes a switching circuit for 1x calculation.

An arithmetic start pulse is input to the input terminal 35, and this signal sets the flip-flop 31, causing the output terminal 36 and the input terminal 33 to which it is connected to go high, so that the shift registers 11 to 17 are fully added. The output of the circuit 30 is read and the calculation is repeated.

The flip-flop 25 is also set by the operation start pulse, and a high level appears at the output terminal 34.

This signal causes the output of the gate 26 to go low, so the shift register 18 is connected to the full adder circuit 300A.
Therefore, the same data is input to the full adder circuit 300A and power a and b, and the addition result is 2.
It becomes a double value and returns to the shift register.

In other words, the doubling operation is repeated.

In this doubling operation, the most significant digit X3 of the divisor entered first is 5.
is repeated until exceeded.

When the value exceeds 5, the flip-flop 25 is reset by the output of the 5 or more detection circuit 24, so the output terminal 34 becomes low level, and the full adder circuit 300A is then read from the shift register 17 (X2). It turns out.

In other words, the input data enters the input input a one digit time earlier, and the digit signal T4 enters the input terminal 31 and the digit signal T8 enters the input terminal 32.
Since O is forcibly entered at the timing of , the contents of the shift register will be multiplied by 1.1.

Data that has been reduced to 1/10 by truncating the least significant digit of the contents of the shift register is read into input a.

This pattern is shown in Table 1. 1st digit, 2nd digit, etc.
......The 9th digit is the timing signal T1. T2. .........T, and shift register X1. X2. X3. The data initially stored in X4 are transferred to shift registers X1, . x2, x3. X4
The initial data in N, , N2°N3. This figure shows the calculation pattern when N4 is used.

If T4 or T8 becomes high level during execution of the 1.1 times operation, the input a of the full adder remains at "O".

Therefore, the addition output S outputs the input b, that is, the data at that time, as is, and the calculation does not proceed.

In this way, the input of T45Tg to the gate 26 prohibits calculation for timing control.

This 1.1 times operation is X4. X3. The contents of X2 are 095
It is repeated until it exceeds 095, and when it exceeds 095,
The output of the detection circuit 23 resets the flip-flop 37 and the output terminal 36 and therefore the input terminal 33 to which it is connected becomes low level, so the operation ends and the shift register retains its own data. Become.

Shift registers X4, x3 .
x2.

The content of Xl represents the value of the reciprocal with significant figures in the form X, X3.X2X1.

If the exponent information of the divisor is ION, the quotient is X4X3.
It will be expressed in the form X2X1×10-N.

In the end, if we execute the 2x operation m times and the 1.1x operation n times, the contents of the shift register where the divisor was initially stored are (X3.X2.Xl) x 2mX (1, 1
) n Also, since the shift register into which the quotient is stored initially contains 1, its contents become 2m×(1,1)n.

The reason why the doubling operation ends when the content of X3 becomes 5 or more is because a carry will always occur next, and 1.1
Do the double operation in X3. To end when the content of X2 becomes 9.5 or more, multiply the value exceeding this value by 1.1 and get
4. X3. X2. The content of Xl is 1.0.4.5 or more, the dividend is 1, and the error from OlO,O becomes large.

That is, the value of this limit is calculated from the following formula, and the exact value is 952.

Let us now try to find the error due to this calculation method.

The correct reciprocal value Y is Y=1000/(X3.X2jX1
It is expressed as

-The result of the calculation based on the invention of strength tree can be expressed as 2m・(1,1)n) That is, 0.95≦(2m−(1,1)n)/Y<1
．． 045 Therefore, it can be said that the calculation error according to the present invention is within ±5%.

The error due to truncation of the fourth digit is less than 1%/time.1.
Since the 1x operation can be performed a maximum of 7 times, in this case, the error will be 7% at worst.

However, it goes without saying that if the number of digits in the calculation is increased, the error due to truncation will be further reduced.

Next, let's calculate the calculation time.

Shift register
and 10.45.

First, the doubling operation ends when the content of X3 becomes 5 or more, so it is performed three times at most.

Also, since the 1, 1 times operation is performed after the content of X3 becomes 5 or more, the number of times is at most 7 (1, 17=1.95).

However, after executing the doubling operation a maximum of 3 times, 1
．． The 1x operation is never executed a maximum of 7 times, and the largest number of operations is 2x operations and 7 1.1x operations, totaling 9.
This means that a maximum of 9 word times are required.

This means that the computation time is reduced to less than 1/3 compared to the 30 word time of the previously mentioned known method.

As shown in FIG. 2, the configuration circuit requires only one shift register, so the number of elements is naturally reduced, and since the operation is simply a repetition of addition, the control circuit is also greatly simplified.

As described above, according to the present invention, the reciprocal is calculated by repeating only the 2x operation and the 1.1x operation, so only one shift register is required, and the control circuit is also significantly simplified. Therefore, the number of elements in the arithmetic circuit is greatly reduced, and the computation time is also significantly shortened, making it possible to provide an integrated circuit at a low cost that can also display the reciprocal of the shutter time, that is, the shutter speed.

The calculation error is also within ±5%, which is sufficiently acceptable for use in cameras.

The circuit according to the present invention can be easily applied not only to reciprocal display but also to calculation of shutter time or aperture control data as required.

In some cases, the calculation result may be output in the form of a shutter speed, and then converted into a shutter time by reciprocal calculation for display purposes, but in this case, the circuit system according to the present invention can be used in exactly the same way. Applicable.

Various modifications can be made to the embodiment circuit described above in detail within the scope of the present invention, and the scope of the present invention extends to all of the claims.

[Brief explanation of drawings]

FIG. 1 is a block diagram for explaining a conventional reciprocal calculation method, and FIG. 2 is a circuit configuration diagram showing an embodiment of the present invention. 1.2,3...operated register, 4,5,6...
... Arithmetic register, 7, 8 ... Shift register, 9 ... Subtraction circuit, 10 ... Subtraction stop detection circuit, 11゜12.13, 14, 15, 16
,17,18゜38...Shift register, 19
, 20, 21. 22...Gate, 23...095 or more detection circuit, 24...5 or more detection circuit, 25,
37...--Flip-flop, 26.27.28
．． 29--...-gate, 30... Full adder circuit.

Claims (1)

[Claims] 1. A storage means for storing a divisor, a quotient, and addition control data, an addition circuit, and select the digit output of the storage means for 2 times operation and 1.1 times operation and input them to the addition circuit. an arithmetic selection circuit; an arithmetic control circuit that switches the arithmetic selection circuit from a 2x arithmetic state to a 1.1x arithmetic state when the data of the most significant digit of a divisor that has been 2x arithmetic becomes 5 or more; 1.1 Equipped with a control circuit that terminates the operation when the content of the data represented by the addition control data in the double operation and the upper two digits of the divisor becomes 095 or more. A reciprocal calculation circuit that calculates the reciprocal.