JPS5839375B2 - Manufacturing method of semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for performing emitter diffusion in a base region formed in a semiconductor substrate.

To perform emitter diffusion, an emitter diffusion source is usually added to the semiconductor substrate after region formation, and the semiconductor substrate is inserted into an emitter diffusion furnace for a predetermined period of time.

An emitter diffusion furnace generally consists of a quartz tube and a heating coil wound around the quartz tube, and a holder in which a plurality of semiconductor substrates are lined up is inserted into the quartz tube for a certain period of time to perform emitter diffusion.

In this case, since the temperature distribution at both ends of the quartz tube has a gradient, the holder is placed in the center of the quartz tube, that is, in a range where the temperature distribution is uniform.

This method is effective for manufacturing general semiconductor devices, which have a fairly deep base depth of 1 μm or more, and therefore require a considerable amount of time for emitter diffusion.

However, in recent years, a so-called quick diffusion method has been proposed, and it has become difficult to manufacture high-quality semiconductor devices without deteriorating the yield unless some modification is made to the above-mentioned method.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to propose a new emitter diffusion method for semiconductor devices to be manufactured by so-called quick diffusion.

In accordance with the above object, the present invention is characterized in that emitter diffusion is performed in a region of the quartz tube with a temperature distribution gradient or within a quartz tube with a temperature distribution gradient. .

This will be explained below with reference to the drawings.

First, regarding the quick diffusion described above, the semiconductor device to be subjected to the quick diffusion has a base depth of 400 mm.
A very shallow shallow base of about 0A (Shallow
Ba5e) ) is a transistor.

When performing emitter diffusion into a shallow base like this, if the emitter diffusion is not completed in a short time, there is a risk that the emitter will penetrate the base, and in reality, the holder must be inserted and removed from the quartz tube in seconds. (20~200
must be done in seconds).

Further, in order to perform rapid emitter diffusion, for example, PSG (phosphosilicate glass) is used as an emitter diffusion source.

FIG. 1A is a cross-sectional view showing a state in which a wafer forming the shallow base transistor is inserted into an emitter diffusion furnace, and FIG. 1B is a graph showing the temperature distribution inside the diffusion furnace. Temperature (Temp2 is taken and shown.

In FIG. 1, 11 is a quartz tube around which a heating coil 12 is wound.

For example, 02 gas is pressurized into the left end 11-L of the quartz tube 11, while the holder 13 is taken in and out from the right end 11-R.

The directions of this loading and unloading are indicated by arrows A and B in the figure.

A wafer 14 of a shallow base transistor to be emitter-diffused is placed on the holder 13 .

However, in order to efficiently perform emitter diffusion, a large number of wafers 14-1, 14-2 are mounted on one holder 13.
...14-N are arranged side by side.

On the other hand, the temperature distribution inside the quartz tube 11 is as shown in FIG. Uniform.

Therefore, it has conventionally been customary to perform emitter diffusion in this central portion C.

Further, by performing emitter diffusion in this central portion C, a uniform and high quality semiconductor device has been ensured.

However, when emitter diffusion is carried out by so-called quick diffusion, it is rather inconvenient to carry out the diffusion using this central portion C.

That is, wafers 14-1, 14-2...
...Since 14-N must be taken in and out of the quartz tube 11, there is a large difference in total absorbed heat between, for example, Waeno 14-1 and Waeno 14-N.
F).

Wafer 1 in front of holder 13, not wafer 1
Wafer 4-1 inevitably spends a longer time in the high-temperature center C, while wafer 14-N at the rear of the holder inevitably spends less time in the high-temperature center C.
It's because it's hot.

In this way, even when wafers are placed in the same quartz tube 11, the total amount of heat absorbed differs depending on the position where they are placed, and in the end, the depth of emitter diffusion with respect to the shallow base is
4 1, 14-2...14-N are different from each other.

The depth of this process ivy diffusion is directly related to the common emitter direct current amplification factor (hFE) of the shallow base transistor, and therefore wafer 14-1.14-2...
- This brings about the inconvenience that hFE is different for each 14-N.

As a result, a uniform product cannot be ensured and the yield rate deteriorates.

In order to solve the above-mentioned disadvantages, the present invention performs emitter diffusion by placing a plurality of wafers to be subjected to emitter diffusion under a temperature distribution that changes almost uniformly along the direction in which these wafers are arranged.

FIG. 2A is a sectional view showing an embodiment to which the present invention is applied, and in particular, shows a case in which a normal emitter diffusion furnace is used without any modification as the emitter diffusion furnace.

Therefore, the residue 1 can be used in a device (furnace) for diffusing the emitter of a general transistor.

FIG. 2B is completely similar to FIG. 1B, and is a graph showing temperature distribution.

As is clear from FIG. 2 Ai- and FIG. 2 B, the wafers 14-1, 14-2...1 on the holder 13
4-N is not in the central part C of the furnace, but is stopped for a predetermined period of time in a temperature gradient part, and is heated.

1 rewafer 14-1.14-2...14-
It is placed under a temperature distribution that changes almost uniformly along the N arrangement direction.

As a result, for each wafer, the applied temperature Ti and the residence time ti
A low applied temperature T1 is applied to the wafer 14-1 with a long residence time tl, and a high applied temperature TN is applied to the wafer 14-N with a short residence time tN. -i (i=1.2...
・N) (considered to be approximately proportional to the product of applied temperature and residence time) TiXti (i=L2
...N) is approximately a constant value.

However, in order to make 'rixti strictly constant, it will be necessary to modify the temperature curve at the temperature gradient section D[;- of FIG. 2B as appropriate.

Although FIG. 2A and FIG. 2B show the case in which a conventional emitter diffusion furnace is used, it is preferable to use an emitter diffusion furnace as explained in FIG. 3 Δbutton and FIG. 3B. .

FIG. 3A is a sectional view showing another embodiment to which the present invention is applied, and FIG. 3B is a graph showing its temperature distribution.

As shown in FIG. 3B, the temperature gradient area shown in FIG. 2B is enlarged as shown in E.

It is clear that as a result of this, the number of waves to be emitter diffused at the same time can be significantly increased.

Inside, the quartz tube 11 is divided into a plurality of heating coils having different heating intensities, such as 31-1, 31-2, 31-3 and 31-4, which are wound around the quartz tube 11 from near the left end to near the right end. A temperature distribution that increases almost uniformly toward .

In this way, the total amount of absorbed heat can be made uniform for all wafers placed on one holder.

As explained above, according to the VC invention, the variation in hFE, which has been a problem in the past due to so-called quick diffusion, is almost eliminated, and the yield of shallow base transistors is further improved.

[Brief explanation of drawings]

Figure 1A is a cross-sectional view showing the emitter diffusion of a wafer in a general emitter diffusion furnace, Figure 1B is a graph showing the temperature distribution inside the furnace, and Figure 2A is a graph showing the temperature distribution in the furnace. 2B is a graph showing the temperature distribution in the furnace; FIG. 3A is a sectional view showing another embodiment to which the present invention is applied. FIG. 3B is the temperature distribution in the furnace. This is a graph showing. In the figure, 11 is a quartz tube, 12 is a quartz tube, and 31-1.31
-2.31-3.31-4, heating coil 13 is a holder, 14-1.14-2. ...14-N is a wafer.

Claims (1)

[Scope of Claims] 1. A method for manufacturing a semiconductor device comprising an emitter diffusion step for forming an emitter region in a semiconductor substrate after forming a base region, wherein a plurality of the above-described emitter diffusion sources are added. After placing the semiconductor substrates on the holder, the plurality of semiconductor substrates on the holder are inserted into an emitter diffusion furnace for heating them, and the plurality of semiconductor substrates are spread along the traveling direction of the holder. The temperature distribution for heating the plurality of semiconductor substrates arranged on a holder and placed in the emitter diffusion furnace here is lowered almost uniformly along the advancing direction of the holder. A method for manufacturing a semiconductor device. 2. A holder on which a plurality of semiconductor substrates are placed is located in the front of the holder in the direction of movement of the emitter diffusion furnace and has a temperature distribution that decreases almost uniformly along the direction of movement of the holder. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is allowed to remain in the temperature gradient portion for a predetermined period of time. 3. The temperature distribution within the emitter diffusion furnace decreases almost uniformly throughout the emitter diffusion furnace along the advancing direction of a holder on which a plurality of semiconductor substrates are placed. A method for manufacturing a semiconductor device.