JPS5840891B2 - data processing circuit - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a data processing circuit for detecting an abnormal state, and in particular, detects the abnormal state from data obtained by sampling voltage, current, etc. of a power system and operates a relay. The present invention relates to a data processing circuit for use in a computer.

The voltage, current, etc. of the power system are sampled at regular intervals, converted to digital data, and then digitally processed. If an abnormality in the power system is detected as a result,
Take appropriate protective measures.

In this case, when detecting data errors and abnormalities, if there is an error in the operation of the data processing circuit, the result will be an incorrect protection measure, ie, a malfunction.

In general, there are two types of malfunctions: those in which something that should have been operated is missed without operating, and one in which something that should not be operated is operated.

Normally, in an electric power system, in order to prevent such malfunctions, the data is processed in a certain way, the results are checked, for example, three times, and if they are all the same, it is assumed to be true and the next process begins. That's what I do.

The operation of the conventional circuit will be explained below with reference to FIG.

FIG. 1) The horizontal axis represents time t, and shows times t1 to t15 at which the current in the power system is sampled at regular intervals.

The sampled current in is of the following equation.

Here, n=1. , 2, 3...h is the sampling time width, which is, for example, every 30 degrees of electrical angle at 60 Hz, that is, 1.39 m5.

The conditions for activating (tripping) the relay due to overcurrent are based on the relationship of the following equation.

Here, N is an arbitrary number, 1n-N indicates data before N samplings, that is, current, and T indicates the tap value.

For example, if N=3, 3ωh=90″, becomes.

The relay is tripped when ■2≧T2,
■2〈Do not trip when T2.

Referring again to FIG. By processing equation (2), time t1
and t4 sampling results a1 are obtained, and in the same manner, results a2 . Obtain a3...

Now, if a system abnormality (indicated by F in FIG. 1) occurs from time t4, this will be the result a4. a5. a(5), so three verifications are obtained for the first time at time t, and the hetrip signal T is output.

From then on (a5゜a6j 27)t (a6t a7.ag
)"', the trip signal T is output every h hours.

By the way, an error in the power system data is caused by, for example, I, +I B + I between the currents l71tIB + IC2Ig of each phase.
This is detected based on the relationship c-3Io=0.

Therefore, when there is an error in the data at time t9, results a6 and a9 essentially have errors and cannot be used.

In the end, in the conventional circuit that performs three consecutive verifications, the result is a10
1 all l a12, we get 3 matches for the first time.

That is, the trip signal T is not output until time t15, which is 11 sample times after time t4 when an abnormality occurs in the power supply system.

As described above, the conventional circuit has the disadvantage that even if there is a temporary data error, there is a considerable delay in detecting an abnormality in the power supply system.

It is clear that these conventional drawbacks are due to the constraint of using consecutive results to perform three checks.

Three matching results in consecutive results an. an-)-t+ ”n
-4-2+ In an+3, for example, if the result an+2 has an error, the result an.

If an+1jan+3 is used, the spirit of the verification, that is, high precision verification, can be sufficiently maintained, and the time required to obtain a verification result can be shortened.

That is, the present invention has been made in order to improve the conventional drawbacks by paying attention to the above-mentioned points.

SUMMARY OF THE INVENTION An object of the present invention is to provide a data processing circuit that can detect an abnormal state of a power system, for example, with high reliability and quickly from data obtained by sampling voltage, current, etc.

, the data processing circuit of the present invention can, for example, calculate the voltage of the power system,
Based on the data obtained by successively sampling analog quantities such as current, an operation is performed to detect an abnormal state between data separated by, for example, three sampling times, and the result is antan+.
When 11"n-1-2, an+3... are input by one person one after another, verification is performed K times, for example 3 times, and the result is a.

Based on N numbers 1, for example, 4 results anyan+t+an
3 sets of results selected from +z lan+3 (arl'
an+1 y an-1-2)+an + an+ I
t an+3 )+ (an+”n+2+an+3)
This will be done at

Therefore, the data processing circuit of the present invention includes three collation circuits that perform each of the three sets of collations, an OR circuit that outputs each output of the collation circuit as a logical sum, and an OR circuit that outputs the outputs of the OR circuit as a logical sum. By providing a one-shot circuit that outputs data continuously for a plurality of sample times, the above-mentioned objective can be achieved in succession.

Hereinafter, an embodiment of the present invention will be explained with reference to the block diagram of FIG. 2.

First, the input terminal 1 is connected to the collation circuits 2-1, 2-2, and 2-3, to which the calculated results an are successively input.

The verification circuits 2-1, 2-2, and 2-3 have storage and verification functions.

That is, the matching circuit 2-1 returns the result an+an+t, t
If a match is obtained after 3 times of matching using an+2,
For example, it outputs '1°'.

Similarly, the result of the matching circuit 2-2 is an l an+2
jan+3'n+2+an+3'tera.

, ar1+1゜an+3 is performed three times, and if there is a match? Outputs 1191.

The outputs of the collation circuits 2-1, 2-2 and 2-3 are input to a three-man OR circuit 3, where a normal OR operation is performed.

The pulse signal P output from the OR circuit 3 is input to a one-shot circuit 4, which is a so-called one-shot multi-by-break circuit, where the input is held for two sampling periods of 2h.

In other words, the one-shot circuit 4 receives the pulse signal P of '1'.
is input, a 2h time pulse is supplied to terminal 5.

Next, the operation will be explained with reference to FIG.

FIG. 3 shows a data string obtained from the power system at a constant sampling period.

In the figure below, C and marks are data when the power grid is in a normal state, ○ marks are data when the power grid is in an abnormal state, × marks are erroneous data, and P marks are pulse signal P.
The occurrence of the trip signal T and the T mark indicate the occurrence of the trip signal T, respectively.

First, at time t1, abnormal state data begins to be sampled, and from time t4, the result a1. This indicates that a2, a3, . . . begin to be input to input terminal 1.

Therefore, since the verification circuit 2-1 obtains verification three times from time t6, it outputs a signal of level "'l", and then the OR circuit 3 repeatedly outputs the pulse signal P from time t6.

As a result, the one-shot circuit 4 and the OR circuit 5 also output signals at the "1" level.

That is, the terminal 5 outputs the trip signal T from time t6).

Next, since there was incorrect data at time t1, the pulse signal P starts from time t7 with a delay of one sampling period.
and trip signal T are output.

In this case, it is substantially the same as if the abnormal state started from time t2.

The third (c) is that the result a2 becomes unusable due to the existence of incorrect data at time t2, and at time t7 when the result a4 is input, the verification circuit 2-3 first detects the "1°" level signal. , and a trip signal T is also output accordingly.

The output of the pulse signal P and trip signal T from time t8 onward is based on the output of the matching circuit 2-1 in the same way as A and A.

In the fourth case, the result a2 becomes unusable because there is a data error at time t3.

Therefore, the pulse signal P and the trip signal T are output from time t7 when the result a4 is input.

In the fifth example E, since there was a data error at time t4, results a1 and a4 become unusable.

Therefore, a trip signal is output from time t8 when result a5 is input.

In the sixth step 1, there was a data error at time t5, so
As a result, a2 and a5 become unusable.

Therefore, at time t7 when the result a4 is input, the collation circuit 2-3 first outputs a signal at the "IM" level.

However, at time t8 when the result a5 is input, the output of the matching circuit 2-1.2-2.2-3 becomes "0" level again, and the pulse signal P is not output, but the output of the one-shot circuit 4 is Since it is at the "1" level, the trip signal T has been continuously output from time t7.

Unless there are three or more consecutive data errors,
This is compensated by the 2h time setting of the one-shot circuit 4.

This eliminates the so-called chuckling or bouncing phenomenon.

The seventh point is at time t6. Because there was an error in the data,
As a result, a3 and a6 become unusable, and the pulse signal P is not output at time t9, but the trip signal T is continuously output from time t7.

In the eighth case, since there was a data error at time t7, pulse signal P is not output at time t7 and tto, but trip signal T is continuously output from time t7.

Figure 4 shows the matching circuit 2-1.2-2.2- shown in Figure 2.
FIG. 3 is a block diagram illustrating details of FIG.

In the matching circuit 2-1, the line 1 led from the input terminal 1
Memories 7 and 8 are connected to a, the memory 7 stores the result an for one sample, and the memory 8 stores the result a for two samples.

, an+, and are constructed of, for example, one-digit and two-digit shift registers, respectively.

The outputs of the memories 7 and 8 and the line 1a are led to an AND circuit 9a, which performs the AND of the three inputs supplied by these.

This is, for example, result a supplied from lla, memory 7 and memory 8, respectively.

+2. an+1 and a. It is to take the logical product of .

The matching circuits 2-2 and 2-3 have the same configuration as the matching circuit 2-1, and the memory 10 stores the results of three samples.
1, an+1jan+2, and is composed of, for example, a 3-digit shift register.

Therefore, the AND circuit 9b in the matching circuit 2-2 produces the result a.

+an+2 and an+s are logically ANDed.

Further, the AND circuit 9c in the matching circuit 2-3 produces the result a.

, ao+1 and a. Take the AND of +3.

When the operation of the present invention is generalized, the result is any
The verification is performed three times with a combination of selecting three results from an+t s an+2t an+a, and the verification is performed three times at the time n+a when the result a is obtained at the latest on the time axis, and the trip signal T is highly reliable. It is output with specificity.

Furthermore, once the trip signal T is output, a trip signal having a continuous level, that is, without a chuck, is continuously output unless verification is impossible two or more times three times in a row.

Of course, the condition when verification cannot be obtained two or more times in a row can be changed by making the holding time of the one-shot circuit 4 longer, and the condition is set to a larger number of times. be able to.

In addition, in the above explanation, an example was shown in which verification is performed three times from four results, but in the present invention, verification is performed three times from N results (N>K
, ≧3), and the respective configurations (one example does not need to be given and are obvious to those skilled in the art).

As explained above, according to the present invention, when detecting an abnormal state in an electric power system by multiple verifications, a sufficient number of pieces of data are given to make it true without requiring that correct data be consecutive. This condition ensures prompt detection without losing high reliability, and also has the effect of eliminating chuck rings.

[Brief explanation of the drawing]

FIG. 1 is a timing diagram for sampling current in the power system, FIG. 2 is a block diagram showing an embodiment of the present invention, and FIG.
This figure is a diagram explaining the operation of FIG. 2, and FIG. 4 is a detailed block diagram of the matching circuit. 2-1.2-2, 2-3... Verification circuit, 3,
5...OR circuit, 4...One-shot circuit, 7,810...Memory, 9...
・Logic product circuit.

Claims (1)

[Claims] 1. In a data processing circuit that performs predetermined calculations on data obtained by successively sampling analog quantities, the results are successively inputted, and the results are collated twice (K2S). Next, a plurality of collation circuits select N results from the inputted N results (N>K) so as to form mutually different combinations and collate them several times, and each output of the collation circuit is 1. A data processing circuit comprising: an input OR circuit; and a one-shot circuit that inputs the output of the OR circuit and holds the output for a plurality of sampling times.゛