JPS5841698B2 - Atsushi Kairo Hoshiki - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a companding circuit system suitable for transmitting, recording and reproducing analog signals.

Conventionally, when audio signals are digitized and transmitted or recorded, a compandor has been used to widen the effective dynamic range of the transmission and recording.

This is especially true when the amplitude distribution is extremely biased toward low levels, such as in speech, by coarsely quantizing large amplitude parts and finely quantizing small parts, thereby improving the signal-to-noise ratio (SN ratio). It is possible to widen the effective dynamic range by keeping it within an allowable range and appropriately increasing the SN ratio in the case of small amplitudes.

The simplest method is to install a non-linear amplifier that suppresses high-amplitude levels and stretches low-amplitude levels before encoding on the transmitting side, compresses the analog amount, and then performs linear encoding.

After encoding, on the receiving side, the original waveform is restored using a non-linear amplifier with characteristics inverse to compression.

A device that performs such compression and expansion is called an analog compandor.

In recent years, with the development of integrated circuit technology, high performance analog to digital converters and digital to analog converters have appeared.

Therefore, if a high-performance analog compandor is developed, a nonlinear encoder and decoder will be easily constructed.

However, if both the compression and expansion sides are in analog format, it is difficult to make a one-to-one correspondence between compression and expansion characteristics.

This is because the compression characteristics and expansion characteristics have errors independently.

If one of the characteristics is completely fixed, the error in the characteristics will be due to only one.

In consideration of the above points, the present invention performs expansion using digital calculations and fixes the expansion characteristics, and performs analog compression on the compression side and then performs analog to digital conversion (hereinafter abbreviated as AD conversion). In this method, only the characteristic error on the compression side needs to be taken into consideration, which is advantageous because there are fewer adjustments to be made in manufacturing.

An example of the present invention is shown below.

First, we will discuss the companding characteristics.

Since the expansion is performed by digital calculation on the expansion side, the companding characteristic becomes a polygonal companding characteristic, and the slope of the polygonal line is set to a power of 2, which simplifies the circuit configuration.

FIG. 1 shows an example of compression characteristics. This characteristic has a slope of 4 times the input amplitude up to % of the maximum amplitude, 2 times the slope from % to R, 2 times the slope from K to %, and 2 times the slope from % to the maximum amplitude.

FIG. 2 shows an example of a circuit configuration that realizes this characteristic, and FIG. 3 shows the operation timing of each part of this circuit.

In FIG. 2, 1 is a sample hold circuit, 2 is a variable amplification circuit whose amplification factor changes according to an external control signal, 3 is a digital/analog conversion circuit, 4 is an AD conversion circuit, 5,
7 is a latch circuit, 6 is a level detection circuit, and 8 is a code conversion circuit.

Next, the operation will be explained.

The input signal applied to terminal 1a is sent to sample hold circuit 1.
During the period indicated by a in Fig. 3,
retain its value.

Then, AD conversion is executed. This AD conversion is assumed to be 12 bits.

This conversion is carried out during the period indicated by b at the beginning of Figure 3.

During this period, the variable amplifier circuit 2 performs 1x amplification according to the command from the level detection circuit 6, and OV is output from the digital-to-analog conversion (hereinafter abbreviated as DA conversion) circuit 3 for generating the reference voltage. There is.

That is, the level of the input signal is detected by directly AD converting the sampled and held values.

The results obtained during this period are read into the latch 5 at the timing shown in FIG.

Based on the result read into the latch 5, a level detection circuit 6 detects in which region the amplitude level of the input signal is.

For example, assume that the input amplitude is in the range from % of the maximum amplitude to K as a result of level detection.

At this time, a command to double the output of the sample and hold circuit 1 is sent from the level detection circuit 6 to the variable amplifier circuit 2, and a command to generate a voltage of H with the maximum amplitude is sent to the reference voltage DA conversion circuit 3. .

By summing the outputs of the variable amplifier circuit 2 and the reference voltage DA conversion circuit 3, an output having the compression characteristic shown in FIG. 1 is obtained.

The period indicated by C at the beginning of FIG. 3 is the period during which this calculation is performed.

Next, the AD conversion is executed again in the period shown by d in FIG. 3, and the result is read into the latch 7 at the timing shown in FIG. 3 2.

This data is the final result after compression.

This result is converted into a second brigadier general code by a code conversion circuit 8, and then transmitted or recorded.

After the final result is read into the latch 7, a command is issued from the level detection circuit 6 to the variable amplifier circuit 2 to amplify the voltage by a factor of 1, and to the reference voltage DA conversion circuit 3 to output oV.

Then, the input signal is sampled and held again, AD conversion is started, and the above operation is repeated.

Also, on the receiving side, the compressed signal is decompressed as described above,
It must be converted back to the original signal.

The expansion characteristics corresponding to the compression characteristics shown in FIG. 1 are as shown in FIG.

In this example, when quantizing on the compression side, the input is multiplied by a maximum of 4 to 1
Since it is 2-bit quantized, the quantization fineness is up to 1.
Corresponds to 4-bit quantization, and the number of decompression bits is 14 bits.
In other words, the output excluding the sign bit is expressed with a maximum of 213 levels of detail.

Since this characteristic has a slope that is a power of 2 and a break point that coincides with the quantization level, it can be expanded by digital calculation.

As can be seen from this characteristic, by examining the upper three bits of the folded binary system excluding the sign bit, it is possible to determine which segment of the broken line the line belongs to.

Now, if the upper 3 bits are "OXX" (X indicates 0 or 1), it indicates that the input level is in the range of 0 to 210, and the playback data is doubled, that is, towards the lower bits. Shifted by 2 bits, the upper 3 bits become “IO”.
In the case of " iio”, the input level is 2.
This indicates that the input level is in the range of 10+29 to 210+29+28, and if the reproduced data is doubled, that is, shifted by 1 bit toward the upper bit, and a constant value of 213+211 is subtracted, and the upper 3 bits are "111", the input level is is 21
It shows that it is in the range of 0 + 29 + 28 to 211, and by shifting the reproduced data 4 times, that is, 2 bits towards the upper bits and subtracting the constant value 2" + 213,
The extension of the characteristics shown in FIG. 4 can be realized.

Here, as a result of the expansion operation, the 1 or 2 bits shifted to the upper bit side are unnecessary because the results of the constant subtraction are all O, but the 1 or 2 bits shifted to the lower bit side are Determine the dynamic range by companding.

In other words, it determines the minimum resolution of nonlinear encoding.

In this embodiment, the number of data bits increases by 2 bits, which corresponds to 14-bit quantization.

FIG. 5 shows an implementation circuit that realizes the expansion characteristics.

11 is a data level detection circuit, 12 is a shift register that stores data, 13 is a counter circuit that generates a clock according to the shift amount of the shift register 12, 14 is a subtraction circuit, 15 and 16 are code conversion circuits, 17 is a DA conversion circuit.

Figure 6 shows the timing chart of this circuit.
A is a clock signal applied to the input terminal 13a of the counter circuit 13; shift register 12
C is the clock signal to the clock terminal 12c of the shift register 12 (this figure shows a 2-bit shift).

2 shows the timing for reading into the latch circuit 16.

Next, the operation of this circuit will be explained.

The upper 4 bits (including the sign bit) of the transmitted or reproduced data input to the terminal 11a are sent to the level detection circuit 1.
1 is input.

In addition, 11 bits of data excluding the sign bit are connected to terminal 12.
The signal is input to the center of the shift register 12 via a.

A 15-bit shift register 12 is used, and O is input to the upper 2 bits and lower 2 bits.

The level detection circuit 11 outputs the amount to be shifted to the counter circuit 13 based on the input data.

Furthermore, the amount to be subtracted is output to the subtraction circuit 14, and the sign bit is output to the code conversion circuit 15.

A clock corresponding to the amount to be shifted is inputted from the counter circuit 13 to the terminal 12c of the shift register 12, and shift-up and shift-down commands are inputted from the level detection circuit 11 to the terminal 12at12b, respectively.

The shift register 12 operates according to these instructions and sends the result to the subtraction circuit 14.

The subtraction circuit 14 calculates the output data of the level detection circuit 11 from the output data of the shift register 12, and sends the result to the code conversion circuit 15.

The code conversion circuit 15 converts the folded double reversed code into a code suitable for input to the DA conversion circuit 17 according to the code bit from the level detection circuit 11.

The result is read into the latch circuit 16 by a command from the counter circuit 13, and is input to the DA conversion circuit 17.

The DA conversion circuit 17 can extract an analog signal corresponding to the input signal.

Currently, AD is expected to be reduced in cost due to the use of IC.
It is thought that the maximum number of bits in a converter will be 12 bits.

An AD converter with a larger number of bits will significantly increase the cost and also reduce the conversion speed.

Therefore, if a dynamic range of 12 bits or more is required using a 12-bit AD converter, it can be achieved at relatively low cost with the circuit configuration described above.

As is clear from the above embodiments, according to the present invention, since the AD converter is commonly used for level detection and AD conversion after analog compression, there is less misalignment at the break point of the broken line of the compression characteristic. Also, on the expansion side, there is no error because the expansion is performed by digital calculation.

Therefore, good companding can be achieved simply by reducing errors on the compression side, making adjustment very easy.

Furthermore, it is possible to transmit and process signals with a good dynamic range at relatively low cost.

[Brief explanation of drawings]

Fig. 1 is a diagram showing the compression characteristics of the compression section using the companding circuit system according to the present invention, Fig. 2 is a configuration diagram of the compression section, Fig. 3 is its timing chart, and Fig. 4 is the expansion of the expansion section. 5 is a diagram showing the characteristics, FIG. 5 is a configuration diagram of the extension section, and FIG. 6 is a timing chart thereof. 1...Sample hold circuit, 2...
Variable amplifier circuit, 4...AD conversion circuit, 6, 11
... Level detection circuit, 15 ... Code conversion circuit, 16 ... Latch circuit, 17 ...
・DA conversion circuit.

Claims (1)

[Claims] 1. Sample-hold means for sample-holding a human signal; the output of the sample-hold means is taken as an input; the input level is divided into a plurality of levels based on a digital control signal; and the output level for the divided input level is nonlinear amplification means for amplifying the nonlinearity of the polygonal characteristic to the output of the sample and hold means, suppressing this level when the input level is high, and extending the level when the input level is small; Analog-to-digital converting means for converting an output into a digital signal; and determining which of the divided input levels the input signal level belongs to from the digital signal output from the analog-to-digital converting means, and based on the result of this determination. control means for outputting the digital control signal to the non-linear amplification means; and a control means for outputting the digital control signal to the non-linear amplification means; and a control means for outputting the digital control signal to the non-linear amplification means; The input signal is set to be output as is, converted into a digital signal by an analog-to-digital conversion means, the level of the input signal is determined from this digital signal by a control means, and the digital control signal is output based on the result of this determination. Amplifying the non-linearity by the non-linear amplification means, obtaining a digital signal by the analog-to-digital conversion means during a second period of the period during which the input signal is sampled and held, and recording or transmitting this digital signal. A code converting means converts the signal into a signal necessary for recording or transmitting the signal, and a level detecting means determines which of the divided levels the signal belongs to based on the upper bits of the reproduced or received signal. The pressure control device is characterized in that it is provided with an expansion means for determining an expansion signal for the reproduced signal in the state of a digital signal based on the judgment result of the level detection means, and a digital-to-analog conversion means for converting the output of the expansion means into an analog signal. Expansion circuit method.