JPS5842486B2 - Initial program load control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an initial program load control method, and more particularly to an initial program load control method that effectively controls initialization in a data processing system where initial program loads are executed due to multiple factors. Regarding control method.

In order to operate a data processing device that is in a stopped state for some reason, an initial program load (hereinafter abbreviated as IPL) is generally required.

The factors for this IPL include the following. (1) IPL instruction by operator's manual operation (operation of switch, button, etc. on the operation panel).

(2) Automatic ■PL when power is turned on.

(3) The software recognizes that its own system is down,
Issues an IPL instruction to its own processor.

(4) When the other system is configured to monitor the own system, the other system detects that the own system is down, and an IPL command is issued from the other system.

In this way, in a system with several IPL factors, when control is transferred to software after IPL, the IP
There are cases where it is desired to change the initial control after L for each IPL factor.

For example, when a control processor is controlling another large mainframe system: (1) IPL at power-on requires an initial reset for both the mainframe system and the control processor;

(2) However, if a failure occurs in the control processor while the system is operating, and the processor on the main body side detects this and sends an IPL command to the control processor, an initial reset is required only on the control processor side. Yes, and I do not want to affect the system on the main body side.

FIG. 1 shows the control target of initial reset at IPL, and FIG.
When a PL instruction or an IPL instruction from an operator is given, both the control processor and the main body system are subject to initial reset control, and Figure 1 shows that the main body system detects a failure in the control processor and An IPL command is sent to indicate that only the control processor is subject to initial reset.

An object of the present invention is to automatically and effectively perform various controls that differ depending on IPL factors, as described above.For this purpose, the present invention has an initial program load control circuit, and A data processing system in which an initial program load is executed is provided with a plurality of flip-flops for storing each of the factors described above, and when a factor that requires an initial program load occurs, a flip-flop corresponding to the factor is set. In addition, the present invention is characterized in that the initial program load control circuit is activated based on the factor.

Hereinafter, the present invention will be explained with reference to the drawings.

FIG. 2 shows an IPL identification control circuit according to an embodiment of the present invention. In the figure, 1 is a flip-flop that holds an IPL identification flag bit, which consists of 4 bits in the embodiment, 2 is an IPL control circuit, and 3 is an OR circuit, 4 is an AND circuit, 5 is a clock signal line, 6 to 9 are IPL factor identification signals IPLI to IPL4 lines, 10 is a reset signal line, 11
1 is a stop signal line, 12 is a clear signal line, 13 is a load signal M, and 14 is a read signal line from the flip-flop 1.

The function of each IPL factor identification signal is as follows.

IPLI is the rising pulse signal of the power ready (POWERREADY) signal when the power is turned on, I
PL2 is a switch signal generated by an operator instruction converted into a pulse signal, IPL3 is a pulse signal created by decoding a command set in a register by software, and IPL4 is an IPL command sent from another system. It is converted into a pulse signal.

It should be noted that the circuit of FIG. 2 may be considered to exist within the initial program load control circuit added to the control processor in FIG.

The operation of the circuit of FIG. 2 is as follows.

First, a reset signal is issued on the reset signal line 10 when a not-ready (NOT) signal is generated from a power supply (not shown).
IREADY) only when the IREADY signal is issued;
The reset signal on the clear signal line 12 from the PL control circuit 2 is designed to prevent the tube from being affected.

A NOT READY signal from the power supply is issued when the power supply is not in a POWERREADY state, ie, at power up and power down.

Therefore, once the power is turned on and immediately before the power ready signal rises, the flip-flop 1 is in a reset state.

Now, when a certain IPL factor occurs, any one of the IPL factor identification signal lines 6 to 9 becomes ``1'', and the corresponding flip-flop 1 is set in synchronization with the clock signal.

At the same time, this IPL factor occurrence is sent to the IPL control circuit 2 through the OR circuit 3.

The IPL control circuit 2 is activated by this, and first issues a stop signal on the stop signal line 11 in order to stop its own processor (control processor in the above example).

Next, a reset signal is issued on the clear signal line 12,
Clears the own processor.

At this time, as described above, the flip-flop 1 holding the IPL identification flag bit is not reset.

After clearing the own processor, load signal line 1
A load signal is issued to the controller 3 to activate a program load circuit (not shown) to execute IPL.

Next, when software control is started after the IPL ends, the contents of the flip-flop 1 are referenced by the program.

As a result of the reference, if the flip-flops corresponding to IPL1 to IPL3 are turned on, the control processor sends an initial reset signal to the main body system shown in FIG.
Initial resets the main system and its own processor.

On the other hand, if the flip-flop corresponding to IPL4 is on, only the own processor is initialized.

Further, when software control is started after completion of IPL by hardware, preparations for the next IPL can be made by reading the IPL identification flag at the initial stage and storing it in a memory or the like.

Furthermore, the IPL identification control circuit according to the present invention is not limited to the embodiment shown in FIG.
It is also possible to adopt a method in which, after holding PLI to IPL4 in a flip-flop, the output of the flip-flop is sent to the IPL control circuit, and the flip-flop is reset by software after the IPL is completed.

As described above, according to the present invention, the flag bit group is
Since the same number of factors as the PL factors are set and the software refers to them after the IPL ends, an excellent effect is achieved in that the initial reset of the system can be dynamically performed by the software.

[Brief explanation of drawings]

FIG. 1 shows a control target for initial reset during IPL, and FIG. 2 shows an IPL identification control circuit according to an embodiment of the present invention. In FIG. 2, 1 is a flip-flop that holds an IPL identification flag bit, 2 is an IPL control circuit, 5 is a clock signal line, 6 to 9 are IPL factor identification signal lines, 10 is a reset signal line, and 11 is a stop signal line. , 12 is a clear signal line, and 13 is a load signal line.

Claims (1)

[Scope of Claims] 1. In a data processing system having an initial program load control circuit and in which initial program load is executed due to a plurality of factors, a plurality of flip-flops are provided to store each of the above factors, and the initial program load is Initial program load control characterized in that when a factor that requires execution occurs, a flip-flop corresponding to the factor is set, and the initial program load control circuit is activated based on the factor. method. 2. The program according to claim 1, wherein the flip-flop is not affected by a reset signal sent along with initial program loading, and is made referenceable by the program. Load control method.