JPS5842625B2 - hand warmer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a double-balanced differential circuit such as an FM multiplex circuit configured in a semiconductor integrated circuit.

In general, when transmitting and receiving radio waves, the FM system is superior to other AM systems in terms of high sound quality and low noise, and it is also capable of stereo broadcasting, making it particularly suitable for music broadcasting.

In the receiving device that receives this FM stereo broadcast,
In addition to low distortion, which is generally required for audio equipment, it is also required to faithfully separate left channel L1 right channel R signals included in the same carrier wave, and the pilot tone method currently in use is required. Conventional methods for demodulating stereo broadcasts include a matrix method in which the (I, -4) signal and (L+R) signal are separated by a filter and calculated, and a switching method in which the L and R signals are obtained by switching subcarriers. was a typical example.

・'・With the above method, it was quite difficult to obtain an excellent degree of separation due to variations in the rise characteristics and temperature characteristics of the diode used for demodulation, and the phase shift of the filter.

Therefore, as a method that currently has excellent performance, there is a coincidence method used in FM multiplex stereo demodulation ICs.

In the above method, the time division circuit is constructed of a double-balanced differential circuit.

According to the above configuration, the differential transistors in the IC have good temperature characteristics because of their good relativity, small gain deviation between the left and right channels, and good separation characteristics because the subcarrier leakage components are canceled out between the left and right channels. Get better.

However, the FM multiplex circuit in which the above configuration is incorporated into a monolithic integrated circuit has a relatively large difference in distortion rate between the right and left channel output signals, and this circuit is used in amplifiers that require a low distortion rate. Since this corresponds to the first stage circuit of the above-mentioned channel, the distortion factor of the entire amplifier depends on the distortion factor of the larger channel, which is not preferable.

The inventors of the present application have solved the above problem in an FM multiplex circuit using a coincidence method using a double-balanced differential circuit shown in FIG. The mass was extracted based on the measurement results.

Further, the inventors of the present application analyzed the cause of the above problem and found that the pattern for configuring the FM multiplex circuit as a monolithic integrated circuit is as shown in FIG.

In the above pattern, the wiring 6 connecting the collector of the transistor and the emitter of transistor q and the wiring 6 connecting the collector of transistor Q and the emitter of transistor Q are obviously longer, and therefore the distributed resistance due to the wiring layer is big.

As a result of experiments, the difference in distortion rate between the left and right channels is mainly due to the collector of transistor Q2, transistor Q5,
It was found that this was due to an imbalance in the distributed resistance due to the difference in the length of the wiring layer leading to the emitter of Qe.

The present invention has been made to solve the above-mentioned problems, and its purpose is to solve the problems described above. The object of this invention is to reduce the difference in distortion rate between two output signals and to lower the distortion rate.

The basic configuration of the present invention for achieving the above object is that in a well-known double-balanced differential circuit configured in a semiconductor integrated circuit, the collector of the first transistor Q1 and the emitter of the third transistor Q3 are connected to each other. The resistance value between the collector of the first transistor Q1 and the emitter of the fourth transistor is made almost equal to the resistance value between the collector of the second transistor Q2 and the emitter of the fifth transistor Q. This is characterized in that the resistance value and the resistance value between the collector of the second transistor Q2 and the emitter of the transistor q in common 6 are made almost equal.

Hereinafter, the present invention will be specifically explained with reference to the drawings along with examples.

Example 1 In configuring the coincidence-based FM multiplex circuit using the double-balanced differential circuit shown in FIG. 1 into a monolithic integrated circuit, the integration pattern was
As shown in the figure, differential transistor Q3. Q5 and Q
4, Q5 have a common collector, so they have the same isolation region, and the differential pair transistors Qs, Q4 and Q5 . In order to share the emitter of transistors Qe, transistors Q1 and Q1 are placed opposite to each other. Q2 is configured by providing separate regions for each.

For each connection, the wiring layer is indicated by a broken line.For example, the wiring route 6 connecting the collector of transistor Q2 shown in the circuit diagram of FIG. 1 to the emitters of differential pair transistors Q and Q is shown in FIG. is transistor Q2
The wiring layer 6 is connected to the midpoint of the wiring layer connecting the collectors of the differential pair transistors Q, , and Qe to the emitters of the differential pair transistors Q, , and Qe.

The connection route numbers in the circuit of FIG. 1 and the wiring layer numbers in the pattern diagram of FIG. 3 correspond.

Furthermore, a differential pair transistor Q3 is provided for crosstalk cancellation in order to improve the degree of isolation. The wiring pattern of Q4 is also a wiring layer connecting differential pair transistors Q3 and Q4 by configuring wiring layer 3 as shown in Figure 3, just as the emitter of differential pair transistor Q5 and Qe is connected to the collector of the transistor. Transistor Q from the midpoint of
1 collector.

As described above, according to the first embodiment of the present invention, the object can be achieved and the effect can be brought about for the following reasons.

As shown in FIG. 3, the wiring layer 6 connected from the collector of the transistor Q2 to the emitters of the differential pair transistors Q5 and Qe is connected from the midpoint of the wiring layer connecting the emitters of the differential pair transistors Q5 and Qe to the transistor differential pair transistors Q5. The approximately equal wiring distributed resistances of the emitters of Qe are equally related to the distortions of the two output signals Lout+Rout, respectively.

Further, a wiring layer 3 is connected from the collector of the transistor Q1 to the emitters of the differential pair transistors Q3 and Q4.
is the same as above, so the differential pair transistor Qs =
The approximately equal wiring distributed resistance of the emitter of Q4 has an equal influence on the distortion of the two output signals Lout+Rout, respectively.

Therefore, a low distortion FM with a small difference in distortion between the right and left channels as shown by lines EL' and E-4 in FIG.
This makes it possible to provide a multiplex circuit.

In addition to the embodiments described above, the present invention can have the following embodiments.

For example, as a method of equalizing the distributed resistances of wiring layers related to the emitters of differential pair transistors, the lengths and widths of wiring layers 3 and 6 may be appropriately set in the semiconductor element pattern shown in FIG. (not shown).

Furthermore, as mentioned above, by adjusting the wiring distribution resistance, it is possible not only to reduce the difference in distortion rate between two output signals, but also to reduce the difference in distortion rate between two output signals. (diffusion resistance, etc.) as differential pair transistors Qa, Q4, Q5-Qa
and the resistance between the collector of the first transistor Q1 and the emitter of the third transistor q and the emitter of the fourth transistor Q1 by these other resistance means. The resistance values between the collector of the second transistor Q2 and the emitter of the fifth transistor Q are made approximately equal, and the resistance values between the collector of the second transistor Q2 and the emitter of the sixth transistor Q2 are made substantially equal. It is very easy to understand from the description of the embodiments already explained that by making the resistance values between the .

The main applicability of the present invention is to reduce the distortion difference between differential outputs in phase detection circuits, synchronous detection circuits, etc. that utilize double-balanced differential circuits.

[Brief explanation of drawings]

FIG. 1 shows a general example of a circuit based on the coincidence method, FIG. 2 shows measurement results of distortion rate characteristics of left and right channels, FIG. 3 shows a pattern diagram of a semiconductor integrated circuit according to the present invention, and FIG. FIG. 4 is a pattern diagram of a conventional semiconductor integrated circuit. 1 to 10...Wiring route, Ql j Q2 t
Qa 1 Q4tQ5- Qa... Differential pair transistor, EL, EC1... Right channel distortion rate characteristic curve, ER, EB:... Left channel distortion rate characteristic curve.

Claims (1)

[Claims] A first transistor Q1 and a second transistor Q2 whose emitters are connected in a differential manner; a third transistor whose emitters are connected in a differential manner and to the collector of said first transistor Q0; Ah transistor Q
8 and a fourth transistor q1, the emitters of which are connected in a differential manner, and a fifth transistor q1 and a sixth transistor Q6 whose emitters are connected to the collector of the second transistor; The first input signal is applied to one base of either of the second transistors Q1 or Q2, and the commonly connected bases of the third and sixth transistors Q3 or the fourth and fifth transistors The input signals of the commonly connected transistors Q4 and Q'5 are applied, and the first output signal is taken out from the commonly connected collectors of the third and fifth transistors Q3 and Q5, In a double-balanced differential circuit configured in a semiconductor integrated circuit such that the second output signal is taken out from the commonly connected collectors of the fourth and sixth transistors Q4-Qe, the collector of the first transistor Q1 is connected to the collector of the first transistor Q1. and the third transistor% above
The resistance value between the emitter of Q and the first transistor Q
The resistance value between the collector of the second transistor Q2 and the emitter of the fifth transistor Q is approximately equal to the resistance value between the collector of the second transistor Q2 and the emitter of the fifth transistor Q. 1. A double-balanced differential circuit constructed on a semiconductor integrated circuit, characterized in that the resistance values between the collector of the second transistor q and the emitter of the sixth transistor are approximately equal.