JPS5842627B2 - Hand tie souchi - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly to a voltage controlled variable resistance semiconductor device (hereinafter referred to as SRG).

First, in order to facilitate understanding of the present invention, this SRG will be explained with reference to FIG.

In the figure, 10 indicates the SRG as a whole, and 1 is a semiconductor substrate of its first conductivity type, N type or P type, which faces the upper surface 1a and is spaced at a predetermined interval L (channel length). holding the first conductivity type as a P-type or N-type source region;
A region 2 and a second region 3 as a drain region are formed, and a gate insulating layer 4 made of, for example, SiO2 is formed on the main surface 1a of the substrate 1 between the secondary regions 2 and 3. A resistor layer 5 is formed on this insulating layer 4.

A source electrode 6 and a drain electrode 7 are ohmically deposited on the regions 2 and 3, respectively, and a first gate electrode 8 and a second gate electrode 9 are deposited on the regions 2 and 3 of the resistor layer 5.
is covered.

In such a configuration, the potential at a point X located an arbitrary distance away from region 2 in the channel is V (usually the gate voltage at point X of the antibody layer 5 is Vc7x), the threshold voltage is vth, Assuming that VG(X) V(X)>vth and the modulation of voltage vth by the substrate potential is sufficiently small, the number N of carriers per unit area in the channel at point X is as follows.

Therefore, the resistance from region 2 of the channel to point X is R(
x), the surface resistance of the channel is ρ8(X), and the carrier mobility is μ, then the following is obtained.

Therefore, if the channel current is 1, then Then, the following formula is obtained.

Therefore, suppose that A, (the necessary and sufficient condition for this to hold is V
(3 (x door V.

o+L■, but the proof is omitted), this (6)
When the equation is substituted into the equation (5) and integrated from x = 0 to L, the equation (5) becomes.

If the potential of the source region 2 is ■8 and the potential of the drain region 3 is ■, then ■=VD−■8, and if the layer quality and thickness of the resistor layer 5 are uniform, , Vo (LV for x), so the potential of the first gate electrode 8 is v8+■oo1 The potential of the second gate electrode 9 is v8+■oo1.

If +VGO°, the above-mentioned necessary and sufficient conditions are satisfied, and therefore, equation (6) is satisfied, and equation (7) becomes ■=β
(vGOVth) ■ holds true.

Kimoto: Therefore, a linear resistance is obtained between the source electrode 2 and the drain electrode 3, and the resistance value is changed to the voltage VG.
It can be variably controlled by O.

That is, the potential of the electrodes 6 and 7°8.9 is set to 8.9. VD, v8
+voo.

(2) If 9+voo, a linear variable impedance characteristic can be obtained between the electrodes 2 and 3.

Figure 2 shows this SRG in symbol form, with S, D
.

G1. G2. Sub is the source, drain, and first
A gate, a second gate, and a semiconductor body region (substrate) are shown.

As is clear from the above, in SRG, a signal component is given to the gate and channel, and the modulation of the channel resistance received by this signal component is reduced to achieve linearity, but normally Since the voltage applied to the substrate (Sub) is a constant voltage such as a ground potential, it is impossible to avoid modulation due to signal components on the substrate side, that is, the substrate effect.

That is, in the above explanation, for convenience of explanation, equation (1) was given assuming that this substrate effect can be ignored, but it must be used in practice.

However, [εS is the dielectric constant of the semiconductor substrate. If the channel current (■) is calculated from this, it becomes as follows. In this case, even if VG (LV for x) is used, (2) does not become a linear function of (2).

Therefore, in general, in order to reduce the coefficient of the substrate effect, the impurity concentration NB of the substrate is reduced, or by increasing VGB and reducing the change in ms V(x)', ■ approaches the linear function of ■. That's what I do.

However, even with this method, it is not possible to obtain sufficiently satisfactory linearity.

The present invention aims to further improve the linearity of this type of SRG by preventing the above-mentioned substrate effect from occurring.

That is, in the present invention, a signal component is applied to the gate and the channel, and at the same time, modulation of the channel resistance due to the body effect is avoided through a signal corresponding to the substrate.

With reference to FIG. 3, an embodiment of the present invention will be described in detail together with an embodiment of the manufacturing method to facilitate understanding thereof.

First, an insulating substrate 11 on which a semiconductor such as silicon can be epitaxially grown is provided.

This insulating substrate 11 may be made of spinel, sapphire, etc., for example.

On this insulating substrate 11, an N-type silicon semiconductor layer 12 having an impurity concentration and a specific resistance of, for example, about 2 to 5 Ω□, which will eventually form a base region, is epitaxially grown to a thickness of about 10 to 15 μm. Figure 3A).

In this case, since crystal defects occur in the epitaxially grown semiconductor layer 12 over a thickness of about 2 to 3 μm from the interface with the insulating substrate 11, the layer is formed to a thickness sufficiently larger than this and the portions without crystal defects are formed. However, the thickness of the semiconductor layer 12 is selected to be thin enough to have an appropriate resistance distribution in the plane direction.

This semiconductor layer 12 has a surface 111, that is, a main surface 12a.
A crystal plane or a crystal plane forming a growth plane of the semiconductor layer 12 can be selected by using spinel as the substrate 11 so as to have 100 crystal planes.

Mesa grooves 13 are formed in this semiconductor layer 12 as necessary to form a plurality of mesas 14, and an insulator that can serve as a diffusion mask for Si02 is formed on the surface of the mesa 14 by chemical vapor deposition or thermal oxidation. Forming layer 15 (FIG. 3C)
.

This insulating layer 15 is first etched by photo-etching.
Then, a second diffusion window is simultaneously opened by photoetching, and through these windows an impurity of the same conductivity type as the first conductivity type of the semiconductor layer 12, that is, the island region 14, for example, N type, is introduced.
The first and second low-resistance regions 16 and 17 are diffused at a high concentration to a depth of about 4μ to maintain a required distance from each other.
(Fig. 3D).

At the same time as this diffusion, the surface of the semiconductor layer within the diffusion windows for forming regions 16 and 17 is oxidized to form an insulating layer again.

Both regions 1 are etched by photoetching the insulating layer 15.
6 and 17 while maintaining the required interval between the first and second
A second conductivity type, ie, P type, impurity is added at a high concentration through the second window to a depth shallower than the diffusion depth of both image resistor regions 16 and 11, for example, about 1 μm. Then, a first region, ie, source region 18, and a second region, ie, drain region 19 are formed (FIG. 3E).

After that, on the part where the gate part is to be formed, that is, on the first and second
The insulating layer 15 between the regions 18 and 19 of
Gate oxidation is applied to a thickness of 200 mm to form a gate insulating layer 20.
(Fig. 3F).

This gate insulating layer 20 covers the first and second regions 18 and 1.
9 so that a part of both ends thereof spans over the top.

A high-resistance layer 21 is deposited on this insulating layer 20 (FIG. 3G).

For this high-resistance layer 21, for example, polycrystalline silicon doped with impurities at a required concentration is deposited to a thickness of, for example, about 0.5 μm by low-temperature chemical vapor deposition, and unnecessary portions are removed by photo-etching. can be formed by removing.

This high-resistance layer 21 has both ends connected to the first and second regions 1.
8 and 19 so as to partially extend over the opposite ends of each other.

Thereafter, the first gate electrode 22 and the second gate electrode 23 are ohmically deposited on the first and second regions 18 and 19 on the high-resistance layer 21.

Furthermore, photoetching is performed on the insulating layer 15 (or the insulating layer 20 if it is formed) to form a first source region 18 and a second drain region 19 outside the gate electrodes 22 and 23.
Windows are opened in parts of the upper and first and second low resistance regions 16 and 17 for electrode attachment, and regions 16 and 18 are formed.
A common source region 24 and a common drain electrode 25 are ohmically deposited on the source regions 19 and 17 (FIG. 3H).
The equal electrodes 22, 23, 24, and 25 can be formed simultaneously by depositing metal on the entire surface by vapor deposition and removing unnecessary portions by photoetching.

The mutually opposing ends of the first and second gate electrodes 21 and 22 are arranged to coincide with the mutually opposing ends of the regions 18 and 19.

Note that when forming an integrated circuit, other SRGs or other circuit elements can be formed on other mesas 14 provided on the common substrate 11, but when forming an SRG single element, each mesa The above-mentioned SRGs are simultaneously formed on each of the mesas 14, and the base body 11 is divided with respect to each mesa 14.

The thus obtained SRG according to the present invention was
gate electrodes 22 and 23, source electrode 24, and drain electrode 25 of each element G1. G2. S
, D are operated with the same voltage relationships as explained in FIGS. 1 and 2, respectively.

In this way, the signal applied to the drain passes through the channel formed under the gate and is also applied to the base region made of the N-type semiconductor layer 14 by the low resistance regions 16 and 11, so that the signal applied to the drain passes through the channel formed under the gate, and is also applied to the base region made of the N-type semiconductor layer 14 by the low resistance regions 16 and 11. In between, the signal components cancel each other out, and modulation by the signal components can be avoided.

In the above example, the high-resistance layer 21 in which impurities are doped in polycrystalline silicon is used, but in manufacturing the high-resistance layer 21, a polycrystalline silicon layer that is not doped with impurities is used. After that, an impurity insulating layer such as oxide Sin doped with an impurity is deposited on this by diffusion etc., and this impurity is diffused into the polycrystalline silicon, or the polycrystalline silicon is formed by thermal diffusion. Impurities can also be doped into silicon.

In this case, the impurity diffusion or thermal diffusion treatment temperature for polycrystalline silicon from the impurity insulating layer is 900°C ~
It can be selected to be around 1000°C.

In this case, if the heat treatment temperature is too high, the threshold voltage vth of the channel will become significantly high.

Furthermore, in the above configuration, the low resistance regions 16 and 17 are
In this case, the depth of the second source region 18 and the drain region 19 is selected to be sufficiently larger than that of the second source region 18 and the drain region 19. In this case, the electric field in the base region 12 can be made uniform.

In addition, in the above example, there is a low resistance region 16 for passing signals.
and 17 are provided in the base region, and in this case, the signal component can be passed to the base region regardless of whether the signal component is high frequency or low frequency. The low resistance regions 16 and 17 can be omitted, as shown in FIG.

That is, in this case, the first and second source regions 18
The structure is such that the base region 12 and the electrodes 24 and 25 are capacitively coupled due to the capacitance of the PN junction between the drain region 19 and the base region 12. In this case, if the signal is a high frequency, the source and drain Since a signal is applied to the channel between the regions and simultaneously applied to the base region 12 through this junction capacitance, the same effect as in the previous embodiment can be obtained.

In this case, since the low resistance regions 16 and 17 can be omitted, it is possible to reduce the size and simplify manufacturing.

FIG. 5 shows still another example of the device of the present invention, in which the gate insulating layer 20 is formed across the source region 18 and drain region 19, and the first and second gate electrodes are omitted, the drain electrode 25 is connected to the high resistance layer 2
This is a case in which a part of it is formed so as to straddle over 1.

The equivalent circuit diagram in this case is as shown in FIG. This is the capacitance formed between the high-resistance element 21 and the high-resistance element 21.

Further, C8 is the capacitance formed between the source electrode 24 and the source region 18, and CGS is the capacitance formed between the source region 18, the channel, and the high-resistance layer 21.

According to such a configuration, when a signal of frequency ω and bias vBi is applied from the drain electrode 25, the signal component is equal to the capacitance C
A signal is applied to the region 19 through D, and is applied to the resistor layer 21 through the capacitor C6d and the contact between the drain electrode 25 and the resistor layer 21.

A DC bias vBi is applied to the drain side of the gate through DC coupling between the drain electrode 25 and the high resistance layer 21.

On the source side, the signal component is taken out through the capacitor C8, and the DC component does not enter.

That is, the bias voltage vBi is used as a channel forming voltage, the signal component having the frequency component ω is coupled to the drain and the source by capacitive coupling, and the resistance between the drain and the source is changed by the bias voltage vBi.

FIG. 7 shows still another example of the device of the present invention, in which a drain electrode 25 is deposited on the drain region 19 via a thin gate insulating layer 20 and a high-resistance layer 21; A similar insulating layer 20 over region 18. This is a case where the source electrode 24 is formed through the .

The equivalent circuit diagram in this case is as shown in FIG. 8, and the parts corresponding to those in FIG. In the case of the structure explained with reference to FIGS. 5 and 7, the capacitance Cpoly formed by 21 is inserted, and the structure described in FIGS. Also, since the second gate electrode can be omitted, there is no need for an area for forming this gate electrode, and there is an advantage that the overall size can be reduced.

Furthermore, since it is not necessary to directly deposit the electrodes 24 and 25 on the drain and source regions, there is no need to open a window for forming these electrodes, and photo-etching, which requires an extremely complicated process associated with opening this window, is not required. Since this can be omitted, the manufacturing process can be greatly simplified.

Furthermore, since the control voltage is changed by the signal bias voltage, the drive circuit can be simplified, and since the number of lead-out terminals can be reduced, connections can be simplified.

Also, the first
Since alignment of the second gate electrode is not required, manufacturing is simplified, and structure and manufacturing can be simplified.

□On each side shown in the figure, the base region/(semiconductor layer) 12 is provided on the insulating base 11, and is formed thinly so as to obtain the required distributed resistance in the plane direction. However, the insulating base 1 can maintain sufficient mechanical strength as a whole.

,, in this case, such an insulating substrate 11.
A similar effect can also be obtained by creating the base region 12 by a PN junction, avoiding the provision of a .

As described above, the device of the present invention allows signal components to pass through the base region, and by doing so, it has been possible to improve the distortion factor by about one order of magnitude or more.

In addition, when using the insulating substrate 11, it is possible to avoid signal leakage even when handling high frequencies, and the frequency characteristics can be significantly improved, and when configuring an integrated circuit, each element can be electrically isolated. This increases the degree of freedom in setting circuit design usage conditions.

[Brief explanation of drawings]

FIG. 1 is an enlarged perspective view showing a partial cross section of a voltage-controlled variable resistance semiconductor element used for explaining the present invention, FIG. 2 is a symbolic diagram thereof, and FIG. 3 is a manufacturing method of an example of the device of the present invention. Process diagram, FIG. 4 is an enlarged sectional view showing another example of the device of the present invention, and FIG.
7 are enlarged sectional views of other sides of the device of the present invention, and FIGS. 6 and 8'' are equivalent circuit diagrams of the device shown in FIGS. 5 and 7. 1j is an insulating circuit. A base body, 12 a semiconductor layer serving as a base region, 18
and 19 are the source region of the first region and the drain region of the second region, 24 and 25 are the source electrode and the drain electrode,
20 is a gate insulating layer, 21 is a high resistance layer, 22 and 23
are first and second gate electrodes, and 16 and 11 are low resistance regions.

Claims (1)

[Claims] 1 First and second regions of a second conductivity type are formed facing an upper surface of a semiconductor substrate region having a first conductivity type with a required distance from each other, and a gap between the first and second regions is formed. An insulating layer is formed on the portion where the channel is to be formed, a resistor layer is formed on the insulating layer, and between the first and second regions and each portion of the resistor layer near the second region. A semiconductor device in which the potential difference between the first and second regions and the base portion near the second region is set to be substantially constant.