JPS5843775B2 - Processor backup system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a processor backup system, and in particular, processors that are not designed with multiplexed back amplifiers in mind can be easily multiplexed to achieve high reliability of the system. It provides a backup system and supports so-called dual mode and duplex mode with the same system configuration.
) mode and the advantages of each mode are utilized as necessary.

DDC (direct digital contact)
rol ) and SPC (set point contr
ol), etc.) High reliability is required for process control computers.

For this reason, reliability has been increased by duplicating central processing units (CPUs: hereinafter referred to as processors), which are central parts (common parts) of the system.

By the way, two methods are generally used for duplication of processors: dual mode and duplex mode.

In dual mode, two processors execute the same process at the same time, and when the main system goes down, they immediately switch to the sub system to act as a backup amplifier.

The subsystem is used only for backup purposes and is not used to perform any other processing even when the main system is operating normally.

However, it has the advantage that bank-up functions such as abnormality detection, switching, and storage of memory contents are almost complete.

On the other hand, in the duplex mode, when both the main and subsystems are normal, the main system executes foreground processing such as DDC, and the subsystem executes another background process.

Then, when a main system town is detected, the sub system interrupts background processing and takes over the foreground processing of the main system.

However, even if there is a discontinuity at the micro level of the program being executed at the time of switching, the continuity of processing at the macro level (back up) cannot be expected as in dual mode. For applications that only require an amplifier (amplifier), the advantage is that the functions of both the main and sub-system processors can be used effectively.

The present invention organically combines the dual mode and duplex mode to take advantage of the advantages of both, and uses a processor designed without the assumption of multiplexed backup, and uses a bank amplifier. The system operates in dual mode to perform backup processing for specific tasks that require it, and for tasks that do not require bank-up, each processor can perform separate processing without receiving backup amplifiers. This makes it possible to effectively utilize the functions of each processor.

FIG. 1 is a configuration explanatory diagram showing one embodiment of the present invention, in which 1 and 2 are processors, and 3 and 4 are main memory units 1-15.
．． 6 is an ink face bus, 7 is a backup unit, 8 is a bus switching circuit, 9 is an ink face bus, io,
ii is an input/output device O. The processor 1 and the main memory unit 3 are coupled by an interface bus 5 to form a first processor system A, and the processor 2 and the main memory unit 4 are coupled by an interface bus 6. It constitutes a second processor system B.

Note that the ink face buses 5 and 6 are driven by an asynchronous confirmation method and include a memory bus, an input/output bus, and the like.

These interface buses 5.6 include the processor 1,
2 and the main memory unit 3.4, each processor system A, B
Specific input/output devices are coupled as necessary, but are not shown.

The ink face bus 9 is also driven by an asynchronous confirmation method, and input/output devices 10 and 11 are combined to form an input/output device system C.

The backup control unit 1 has a function of commonly interrupting and synchronizing each processor 1.2, and in a synchronized state, each processor 1, 2 commonly interrupts a predetermined input/output device 10 or 11 of the input/output device system C. Processor system A to access.

The function of collating the signals transmitted to each interface bus 5, 6 of B and controlling the access of each processor 1 and 2 according to the result, and the function of controlling the access of the predetermined input/output equipment of input/output equipment system C in the synchronized state. 10 or 11, and includes functions for specifying processor 1 or 3 to access processor 10 or 11.
6 are commonly connected.

That is, the backup control unit 1 includes a synchronous interrupt circuit 71, a bus verification circuit γ2, a control status register 73, and the like.

The synchronous interrupt circuit γ1 has a function of commonly applying an interrupt to each of the processors 1 and 2 of the processor systems A and H to synchronize both processors 1 and 2.

Generally, when an interrupt request to a processor is accepted,
A polling signal is sent from the processor to search for an interrupt cause, but the synchronous interrupt circuit 11 returns an ink face signal that controls polling only when correctly polled from both systems A and B. It is composed of

Also, when polling is done correctly from both systems, the output signal of the synchronous mode flip-flop (not shown) is set to "1".
” can also be set.

In the synchronized state, the bus verification circuit 12 includes both systems A,
When the processors 1 and 3 of B access the common input/output device 10 or 11 of the input/output device system C, the interface buses 5 and 6 of both systems A and B at the significant timing of the ink face signal at the time of access. Check whether the above M coarse signals match, and only when they match, return a response signal to each bus 5.
Alternatively, it controls execution of access to 11.

Note that when the information signals do not match, no response signal is returned to the buses 5, 6, so each processor 1, 3 terminates its access after a predetermined period of time, generates a non-response interrupt, and performs self-diagnosis.

In the synchronized state, processors 1 and 2 of both systems A and B execute the same program, but since they are independent processors, the oscillation frequency of each source clock differs, so there is a slight difference in the execution speed. makes a difference.

However, in the present invention, by utilizing the fact that the interface buses 5 and 6 are of an asynchronous confirmation method, the programs (
This aims to synchronize the instruction execution level).

The control status register 13 is a register that specifies which processor has the right to access (control) the input/output device 10 or 11 of the input/output device system C.

The bus switching circuit 8 is controlled by the status signal of this register γ3.

Incidentally, mismatch information when a mismatch occurs in input/output device access of each processor 1 and 2 in a synchronized state is also registered in this register.

The contents of this register γ3 can be read independently from each processor 1 and 2.

Furthermore, the control authority over the input/output equipment is initialized to a predetermined processor 1 or 2 when power is turned on. For example, if processor 1 goes down while processor 1 has the control authority, the control authority is automatically transferred by a down detection signal. The process is automatically transferred to processor 3.

Furthermore, a manual maintenance switch can be added to forcibly set control authority to a predetermined processor 1 or 2.

The bus switching circuit 8 has a function of selectively connecting the interface bus 5 or 6 of a predetermined processor system A or B to the interface bus 9 of the input/output equipment system C according to the control right designation signal of the backup control unit 1. In this embodiment, an example is shown in which a logic circuit element is used.

As a result, the predetermined input/output device 10 or 11 is accessed from the processor 1 or 2 having control authority.

FIG. 2 is an explanatory diagram of the operational concept of the system configured as described above.

The processors 1.2 of each processor system A, B may normally execute different tasks TA=TB completely independently.

When a synchronous interrupt occurs and the synchronous mode S is entered, the processors 1 and 2 are synchronized by the synchronous interrupt and execute a common specific task T8.

In this synchronous mode S, the common input/output device 10 or 11 is accessed, but the address information and data information of each access from each processor 1, 2 are compared and verified by the bus verification circuit γ2 to ensure that they match. Since access to the predetermined input/output device 10 or 11 is executed only at the time, the processors 1 and 2 perform back-amplification processing in a so-called dual mode.

This synchronization mode S is canceled at the end of the specific task Ts.

When the processing of task Ts is completed and the synchronization mode is released,
Each processor 1゜2 again has its own task TA,
Processes TB.

Here, since the DDC program and the like are generally activated periodically by a one-second clock interrupt or the like, the synchronous interrupt and the clock can be used together.

FIG. 3 is a detailed explanatory diagram of the ink face operation in the synchronous mode S in FIG. 2.

Sl: Processor 1 executing completely independent and separate processing
, 2, the synchronous interrupt request signal PREQ is simultaneously sent from the synchronous interrupt circuit 71. 082A, 82B: When the processors 1 and 2 receive the respective signals PREQ,
A control signal PDACK for polling the interrupt factor is sent to each synchronous interrupt circuit 11.

Since the processors 1 and 2 are executing different processes, the control signals PDACK from the processors 1 and 2 that reach the synchronous interrupt circuit 11 have a time base.

S3: When the synchronous interrupt circuit 11 receives more and more control signals PDACK from the processors 1 and 2, it simultaneously sends response signals PDATI to the processors 1 and 2 for the first time, and the processors 1 and 2 respectively Polling operations for synchronous interrupts are completed almost simultaneously and the synchronous mode is entered.

At this point, the output of the synchronous mode flip-flop is 1”
is set to

In synchronous mode, processors 1 and 2 are preprogrammed to execute the same program.

That is, this can be achieved by making the program started by a synchronous interrupt and the data (memory contents) used by that program the same.

Note that if the control signal PDACK is not sent from the processors 1 and 2 in response to the synchronous interrupt request of Sl, the response signal PDATI will not be sent from the interrupt request side. A non-response interrupt to polling occurs and the polling sequence is interrupted.

S4A, 84B: When the processors 1 and 2 enter the synchronous mode and execute the same program, and an access command to the common input/output device 10 or 11 is executed, the common input/output device appears on the interface bus 5, 6. An access sequence for 10 or 11 occurs.

That is, address information for a predetermined input/output device 10 or 11 is sent to the interface buses 5, 6,
Ink face control signal 5E that informs the timing
LO is sent from processors 1 and 2.

Although the processors 1 and 2 are in synchronous operation due to the synchronous interrupt, their machine cycles are not completely the same, so there is some difference in the timing of the control signal 5ELO of S4A and 84B.

B5: When the bus verification circuit γ2 learns that the address information given by the control signal 5ELO is for a common input/output device, it confirms that the control signal 5ELO from the processor 1.2 arrives, and at that time bus 5,
A response signal R8P to the control signal 5ELO is sent to the processors 1 and 2 only if they match.

S6A, 86B: Processors 1 and 2 send response signal R8P
When it receives the input/output device 10 or 11, it sends the write data for the input/output device 10 or 11 to the buses 5 and 6, and sends out an interface control signal DAT O to notify that fact.

It should be noted that the timings of the control signals DATO of S6A and 86B may also differ to some extent due to the respective machine cycles.

Sl: The bus matching circuit γ2 receives the control signal DATO from the processors 1 and 2, and writes to the common input/output device 10 or 11 only when the data information on the buses 5 and 6 match at that timing. When the execution is completed, a signal DAT1 is sent to the processors 1 and 2.

When the processors 1 and 2 receive the signal DAT1, they complete their respective input/output device access sequences that started with the sending of the control signal 5ELO.

Note that in 81 to S1 above, an example of a write sequence for the common input/output device 10 or 11 has been described, but the read sequence also includes synchronization of the ink face sequence, collation of address information and data information, etc. .

S8A, 58B-8l 1 : The access sequence for the synchronous mode flip-flop is executed in exactly the same manner as S4A, 84B-8γ, and the synchronous mode is released.

By the way, in the above embodiment, in the synchronous mode state,
An example in which the output signal of a synchronous mode flip-flop is set to '1' is explained.

By doing this, the input/output devices 10.11 of input/output device system C can be accessed independently by processor systems A or B, and
It is possible to identify when a backup is accessed.

Note that if the input/output devices 10.11 are always backed up by the processor systems A and B, the output signal of the synchronous mode flip-flop does not necessarily need to be set to 1''.

In addition, in the above embodiment, the two processor systems A and B have two
Although an example of a multiplexed backup has been described, for example, a multiplexed backup system can also be realized by using three processor systems and configuring so that access is executed when the signals of at least two systems match.

As is clear from the above, according to the present invention, even if a processor is not designed on the premise of multiplexed backup, multiplexed backup can be easily realized, and the system can be highly reliable.

Moreover, so-called dual mode and duplex mode can be realized in the same system, and the advantages of each can be utilized as necessary.

In particular, in dual mode, the validity of accesses to common input/output devices is checked against the interface bus level, so abnormalities (mismatches) can be detected faster and reliability of input/output device accesses is increased. .

In addition, in the case of duplex mode, each processor can perform completely unique processing, and in addition to self-diagnosis, each processor can also run programs that diagnose the other, improving the diagnostic functions necessary for multiplexing. I can do it.

Furthermore, in the present invention, the synchronous interrupt circuit that also serves as a clock interrupt is a common part of the system, but by providing periodicity to the synchronous interrupt, it is possible to check the synchronous interrupt circuit by each processor. This also has the effect of providing a certain degree of diagnostic function for failures in common parts.

[Brief explanation of drawings]

FIG. 1 is a configuration explanatory diagram showing an embodiment of the present invention, FIG. 2 is an explanatory diagram of the operational concept of the system in FIG. 1, and FIG. 3 is a detailed explanation of the ink face operation in synchronous mode S in FIG. 2. It is a diagram. 1.2... Processor, 3,4... Main memory unit, 5.6... Interface bus, γ... Back amplifier unit, γ1... Synchronous interrupt circuit, γ2... Bus Verification circuit, γ3... Control status register, 8... Bus switching circuit, 9... Interface bus, 10.11
...Input/output equipment, A, B...Processor system, C...
・Input/output equipment system.

Claims (1)

[Claims] 1 Multiple sets of processor systems in which predetermined component devices including processors are connected by an interface bus with an asynchronous confirmation method, and predetermined input/output devices with an interface bus with an asynchronous confirmation method? A function that commonly interrupts and synchronizes the integrated input/output device system and each processor, and a function that allows each processor to commonly access a predetermined input/output device of the input/output device system in the synchronized state. A function that collates the information signals transmitted to each interface bus and controls access of each processor according to the result, and a function that specifies which processor accesses a specified input/output device of the input/output device system in a synchronized state. A backup control unit that includes a backup control unit that is commonly connected to each processor-related interface bus, and selectively connects a predetermined processor-related interface bus to the input/output device-related interface bus according to the specifications of this backup amplifier control unit. The bus switching circuit is connected to a bus switching circuit, and performs backup processing using the synchronous interrupt for specific tasks that require bank-up, and allows each processor to receive backup for tasks that do not require backup. A processor backup system characterized in that processing is performed independently.