JPS5843906B2 - Semiconductor integrated circuit and its circuit programming method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a programmable semiconductor integrated circuit and a method for using the same, that is, a method for programming a programmable integrated circuit.

More specifically, the semiconductor integrated circuit of the present invention is a device having a programming wiring within the circuit wiring, and the circuit programming method of the present invention is performed by irradiating the programming wiring with an energy spot such as a laser spot. .

A fabricated integrated circuit chip can be programmed by cutting or shorting some of the integrated circuit wiring.

Conventionally, this programming method has been used to program, for example, a read-only memory (CROM), and has recently been used to repair defective cells in memory elements.

These conventional methods usually use the following method.

(1) Fuse the fuse with electric current and cut the wiring.

(2) Optical energy is applied externally using a laser pulse to cut the wiring.

FIG. 1 shows an S102 layer 2 deposited on a silicon substrate 3.
A laser spot 4 is irradiated onto the polycrystalline silicon layer or A1 layer 1 which is electrically isolated from the substrate.
, this is a method of programming by cutting it (FIG. 1B).

As an example of this, by R, P. Cenker et al.
979ISSCCDigest of Technic
al Papets), experimental results have been shown in which the wiring of the decoder of a MOS memory is changed, the decoder connected to a defective cell of the memory is disconnected, and the decoder is replaced with a non-defective cell connected to a dummy decoder.

However, this method of cutting elements has the following drawbacks.

(1) A large amount of laser energy is required, and melted polycrystalline Si or Al tends to damage nearby Si02 films, and the laser beam tends to damage the substrate.

For this reason, a sufficient margin is required in the layout, resulting in a large area.

(2) There are cases where cutting alone is insufficient and short-circuiting is more advantageous in terms of the area occupied by the chip.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to create a wiring structure and process that can be programmed using a heating method using a laser, an electron beam, etc., in a small margin area, and that does not impair the reliability or damage the appearance of the device. To propose a law.

Therefore, in order to achieve the above object, the device and method proposed by the present invention basically realize a short circuit.

By the way, it goes without saying that a certain desired function can be achieved with the present invention alone, but by using both cutting and shorting with the same device that performs conventional cutting, extremely flexible wiring can be achieved. Changes are also possible.

The present invention will be explained below using specific examples.

This will be explained with reference to FIG.

FIG. 2A shows two n+ type polycrystalline Si (polyS
i) layers 5, 7 have a very high resistance (e.g. 100 k)
This is a programming wiring structure in which the wirings face each other with a layer 6 made of a polycrystalline Si layer (which may or may not be doped with impurities) interposed therebetween.

By irradiating this with a laser spot such as 10 or an electron beam spot and giving sufficient energy, diffusion is caused from the n+ type layers 5 and 7, and as shown in FIG. 2B, the high resistance layer 6 is converted into a low resistance layer 11.

As a result of the above, before irradiation, n+ type layers 5 and 7 are in a non-conducting state,
The programming wiring was inactive, but after irradiation, n
The +-type layers 5 and 7 are changed to a conductive state, and the programming wiring is activated.

In FIG. 2, the opposing low resistance layer is an n+ type layer, but it goes without saying that it may be a p+ type layer.

The results of an experiment in which the structure shown in FIG. 2A was irradiated with a laser will be shown below.

In the experiment, an n+ i n+ tank structure polycrystalline silicon layer was used.

The spacing between the n+ type layers is approximately 3 μm, and the width is 3 μm.

The n+ type layer is doped with phosphorus or arsenic and has an impurity concentration of 1018/
CrfL-3 or higher.

This structure has a resistance value of 1010 g or more before laser irradiation, which is sufficiently high compared to a transistor in an integrated circuit, and can be considered to be globally insulated.

When this structure was irradiated from above with a laser beam having a diameter of 7 μm and an energy of 5×10 7 W/crA for 200 Hsec in a state that applied to the n+ type layer, the resistance value changed to 5008 as shown in FIG.

In FIG. 3, 301 shows the current-voltage characteristics before laser irradiation (resistance value 1010t!Q or more), and 302 shows the characteristics after laser irradiation (resistance value is 501).

This is a change of 106 or more in resistance value, and can be considered to be a complete short circuit.

The laser energy required above was 17100 or less of the energy required to cut the Al wire, and 1/10 or less of the energy required to cut the polycrystalline Si.

In addition, the underlying Si, S s 02 films, and polycrystalline S
There was also little damage to the SiO2, SiN, etc. layers deposited on the surface of the i.

As described above, the results of experiments revealed that this method has the following characteristics.

(1) The change in resistance value is 106 or more, and an insulator or a high-resistance material can be used as a conductor or a low-resistance material.

(2) It uses less energy and requires only a low-power, inexpensive laser light source.

(3) Do not damage the base or the insulating film deposited for passivation.

Next, a semiconductor integrated circuit used in the circuit programming method of the present invention will be explained.

FIG. 4 shows a memory decoder that can repair defective bits by applying the present invention.

Here, 101 to 121 are P-channel insulated gate field effect transistors (MOS transistors), 122 to 14
8 is an N-channel MOS transistor.

149 to 171 are n+ i-n+ tank structure polycrystalline Si
(poly-Si) layer, and indicates that the laser is irradiated to the position marked with an x.

Further, Vcc is a power supply voltage terminal. The function of this decoder is to output address signals a from address lines 173 to 184.

-a5 p ao” According to the high and low level information of a5, a plurality of word lines 185, 186, 187° 188, . . .
. . . One of them is selected and set to a high level.

In the example shown here, since the address signal is a□-25, one word line is selected from 2'=64 word lines.

Here, four word lines 185 to 188 are shown for simplicity.

Here, 189 and 190 are spare word lines connected to spare memory cells, which are normally at a low level unless there is a defective memory cell.

Here, if there is a defective memory cell connected to word line 187 or 188, n+-1-n in FIG.
Irradiate the laser to the + layer marked with an x.

Since the word line 150 is short-circuited and the gates of the transistors 141 and 143 are at the power supply voltage Vcc level, the word line 187
, 188 are no longer activated.

Also, 152.154.156, 159, 160, 16
2.164.166.169 and 170 are short-circuited, this preliminary decoder circuit 401 is activated, and transistor 106 is activated.
~110, and transistors 127~131,11
This is the same connection as the decoder made up of 8, 119, 141 to 144.

In addition, due to the short circuit of 151, the word line 189
, 190 will replace the word lines 187, 188.

Here, the resistor 172 is a resistor for keeping the word lines 189 and 190 at a low level when the preliminary decoder is not used, and it is sufficient if it is thicker than the sum of the series resistances of the transistors 132 to 136.

As shown above, defective bits in memory can be corrected.

Although this embodiment uses only short circuits, it is also possible to open circuits by increasing the energy using the same laser device, so it goes without saying that even if these are used together, wiring can be made more freely.

An example of this is shown in FIG.

In FIG. 5, reference numerals 191, 192 and 193 are nl-type polycrystalline silicon layers, and the locations 192 and 193 marked with x are cut by laser irradiation, and the same circuit program as in FIG. 4 is performed.

The basic functions are exactly the same as those shown in FIG. 4, so their explanation will be omitted.

As described above, the resistor 172 shown in FIG. 4 can be omitted by using the open portion formed by laser irradiation.

In the above example, the resistance layers on both sides were of the same type, such as n''-1-n+, p+ i p+, but as shown in FIG. When a polycrystalline silicon layer structure having a high resistance layer (i layer) 14 between opposing n+ type layer 13 and p+ type layer 15 is irradiated with a laser spot 18 under the same conditions as in the embodiment shown in FIG. As shown in Figure 6B, the n+ type layer (impurity concentration 1018/c
rn” or higher) and p+ type layer (impurity concentration 1018/
crrL' or more), an n-type layer 16 and an n-type layer 17 are formed, and a pn junction is formed.

Therefore, when the width is 3 μm and the n+-p+ interval is 3 μm, the current-voltage characteristics change as shown in FIG. 7 (701: before laser irradiation, 702: after laser irradiation).

By using this pnw synthesis, optically writable read-only memory or Programm
Able Logic Array (PLA) can be formed as shown in the plan view A and circuit diagram B of FIG.

Here, word lines 48 and 49 are p+ type poly-Si layers, and n+ type poly-Si layers facing each other via i-layers 34 to 41
Connected to layers 20-26.

This n+ type layer is connected to Al data lines 27 to 33 through through holes.

By irradiating locations 34 to 37 of this structure with a laser, a diode can be obtained and a PLA can be constructed.

As shown above, the present invention allows wiring of integrated circuits with an extremely high degree of freedom and has high reliability.

Therefore, by manufacturing a standard chip without modifying the Si process step and applying the wiring process of the present invention to the already manufactured wafer, a logic integrated circuit using the mask slicing method that configures a logic circuit, Needless to say, it can automatically program microcomputers, correct defective bits in memory, and is suitable for many applications in digital integrated circuits.

Furthermore, if the present invention is applied to testing analog amplifiers, etc., after testing with the feedback loop disconnected,
It goes without saying that the present invention can be widely applied to analog integrated circuits, such as closing feedback loops, making testing extremely easy, and also trimming input offset voltages of analog amplifiers and D/A converters.

In the above embodiments, an example was shown in which a polycrystalline Si layer was used as the programming wiring, but it is of course possible to use single-crystal Si or even a semiconductor layer other than Si.

[Brief explanation of drawings]

Fig. 1 is a principle diagram showing a conventional method of cutting wiring by laser spot irradiation, Fig. 2 is a diagram showing an embodiment of the present invention in which programming wiring is short-circuited by laser spot irradiation, and Fig. 3 is a diagram showing the method of cutting wiring by laser spot irradiation. FIG. 4 is a diagram showing the current-voltage characteristics of the programming wiring before and after laser irradiation in FIG. 6 is a diagram showing an embodiment of a memory decoder circuit that can repair defective bits by shorting and cutting programming wiring by laser spot irradiation according to the present invention. FIG. A diagram showing an embodiment of the present invention in which a pn junction is formed in the wiring, FIG. 7 is a diagram showing the current-voltage characteristics of the programming wiring before and after laser irradiation in FIG. 6, and FIG. FIG. 2 is a diagram showing an example of a planar pattern and a circuit configuration showing a method of configuring an applied programmable logic array (PLA). 1... Wiring layer (Al, polycrystalline Si, etc.), 2, 8
...Insulating film (8102 etc.), 3,9...
・Substrate (Si, etc.), 4,10...Energy beam spot (laser spot, electron beam spot, etc.), 5゜7...High impurity concentration (low resistance) polycrystalline Si layer , 6...High resistance polycrystalline Si layer (i layer)
, 11... Impurity-introduced (low resistance) polycrystalline Si layer, 101-121... P-channel insulated gate field effect transistor, 122-148...N
Channel insulated gate field effect transistor, 149~
171...n+i-n+ structure polycrystalline silicon layer, 172...Resistance, 173-184...
・Address line, 185-188...Word line,
189, 190... Reserve word line, 19L19
2,193...n+ type polycrystalline silicon layer, 40
1... Backup decoder.

Claims (1)

[Scope of Claims] 1. In a semiconductor integrated circuit having a wiring layer for circuit programming on an insulating film provided on a semiconductor substrate, the wiring layer for circuit programming has two low-resistance parts connected to each other via a high-resistance part. 1. A semiconductor integrated circuit comprising semiconductor layers facing each other and arranged so that the circuit configuration of the semiconductor integrated circuit is changed by reducing the resistance value of the high resistance portion. 2. The semiconductor integrated circuit according to claim 1, wherein the two low resistance parts are doped with impurities of the same conductivity type at a high concentration. 3. The semiconductor integrated circuit according to claim 1, wherein the two low resistance parts are doped with impurities of different conductivity types at high concentrations. 4. The semiconductor integrated circuit according to claim 1, 2, or 3, wherein one of the low resistance parts is connected to a preliminary circuit, and the other is connected to the circuit main body. 5. The semiconductor integrated circuit has a cutting wiring made of either a semiconductor layer or a metal layer as the programming wiring layer, and the circuit configuration of the semiconductor integrated circuit is changed by cutting the cutting wiring. Claim 1, characterized in that the cutting wiring is arranged so as to
The semiconductor integrated circuit according to item 1 or 4. 6 Claims 1, 2, 3, and 4, characterized in that the semiconductor layer is made of a polycrystalline Si layer.
Or the semiconductor integrated circuit according to item 5. 7. When programming a semiconductor integrated circuit having a programming wiring layer made of a semiconductor layer in which two low resistance parts face each other via a high resistance part on an insulating film provided on a semiconductor substrate, The circuit configuration of the semiconductor integrated circuit is changed by irradiating the semiconductor layer with an energy beam spot to diffuse impurities from the low resistance part to the high resistance part and activating the programming wiring layer. A circuit programming method for a semiconductor integrated circuit, characterized in that: 8 The above two low resistance parts are doped with impurities of the same conductivity type at a high concentration, and by diffusing the impurity from the low resistance part to the high resistance part by the energy beam spot irradiation, the above two low resistance parts are doped. 8. A circuit programming method for a semiconductor integrated circuit according to claim 7, characterized in that two low resistance parts are short-circuited. 9 The two low resistance parts are doped with impurities of different conductivity types at a high concentration, and the energy beam spot irradiation diffuses the impurities from the low resistance part to the high resistance part, thereby increasing the high resistance. Claim 7, characterized in that the part is converted into a PN junction diode.
A circuit programming method for a semiconductor integrated circuit as described in Section 1. 10 One of the low resistance parts is connected to a preliminary circuit, and the other is connected to the circuit main body, and the preliminary circuit is electrically connected to the circuit main body by the energy beam spot irradiation. Claims 7 and 8
10. A circuit programming method for a semiconductor integrated circuit according to item 9 or 9. 11 The semiconductor integrated circuit has a cutting wiring made of either a semiconductor layer or a metal layer, and the circuit main body is cut by irradiating the cutting wiring with an energy beam spot. 11. A circuit programming method for a semiconductor integrated circuit according to claim 10, wherein the defective portion is inactivated. 12. Claims 7, 8, 9, and 10, characterized in that the semiconductor layer is made of polycrystalline silicon.
12. A circuit programming method for a semiconductor integrated circuit according to item 1 or 11. 13. Claims 1, 8, 9, 10, 11, or 12, wherein the energy beam is at least one of a laser beam and an electron beam. A circuit programming method for a semiconductor integrated circuit as described.