JPS584461B2 - Manufacturing method of MIS type semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing an MIS type semiconductor device, and is primarily directed to a method for manufacturing a silicon gate MIS type ROM having a ROM (read only memory) pit pattern writing process.

In the silicon gate MIS type ROM according to the present invention, a diffusion layer formed on a silicon substrate and having a conductivity type different from that of the substrate is used as a GND (ground) line, a polycrystalline silicon layer on the substrate is used as an input line, and The aluminum layers that intersect with each other are used as output lines, silicon gate MIS elements are provided at some intersections of these lines, and information is written by selecting the position of the element.

That is, the manufacturing process of the present invention is shown in FIG. 1 (a, b...
. . is a cross section in the output line direction of a portion where a silicon gate MIS element is formed, and a', b' . . . is a cross section in an output line direction of a portion where a silicon gate MIS element is not formed.

(a) forming a thick thermal oxide film 2 on a silicon substrate 1; (b)
Remove the thermal oxide film on the part that will become the drain connected to the GND line and the output part, (c) Thin gate oxide film 3
(d) polycrystalline silicon layer 4 is formed on the entire surface, (e
) Gate 4a and input line 4b by selective etching
Formation, simultaneously opening a window for GND line formation, (f) GN
Formation of diffusion layers 5 and 6 that will become the D line and drain, (
g) Form an oxide film 7 on the entire surface, open a window in the oxide film on the surface of the diffusion layer, then evaporate aluminum 8 on the entire surface, form an output line by selective etching, (h) oxidize silicon on the entire surface by decomposing monosilane. The writing of the ROM pattern is done by changing the mask used when partially removing the thermal oxide film in step (b) so as not to create an output part in the part 1a, for example. It is something to do.

FIG. 2 equivalently represents a ROM manufactured by the above process.

FIG. 3 shows a plan view of the ROM shown in FIG. 2 above,
The A-A cross section is the cross section shown in Figure 1 a to h, and B
The -B cross section is the cross section shown in FIGS. 1a' to 1h'.

According to the method of the present invention as described above, information can be written depending on whether or not the oxide film on the drain part is removed at the same time as the oxide film on the source part, so the manufacturing method of silicon gate MIS elements using the self-alignment method can be used as is. You can write by

The present invention can be similarly applied to writing information in other MIS type semiconductor devices using a self-alignment type, such as a molybdenum gate MIS type, in addition to the silicon gate MIS type.

[Brief explanation of drawings]

FIG. 1 is a manufacturing process diagram according to the ROM manufacturing method of the present invention, where a to h are cross-sectional views taken along the output line of the portion where a silicon gate MIS element is formed, and a' to h' are cross-sectional views along the output line where a silicon gate MIS element is not formed. 2 is a sectional view taken along the output line of the portion, and FIG. 2 is an equivalent circuit diagram of a ROM manufactured by the method shown in FIG. 1. FIG. 3 is a plan view of the ROM shown in FIG. 2. 1... Silicon substrate, 2... Thermal oxide film, 3... Gate oxide film, 4... Polycrystalline silicon layer (input line)
, 5, 6...diffusion layer, 7...CVD oxide film, 8...
・Aluminum wiring (output line), 9... oxide film,
10...Contact hole.

Claims (1)

[Claims] 1 A gate electrode conductor layer, which is an input line, is extended on a semiconductor substrate of a first conductivity type via an insulating film, and is adjacent to a common semiconductor layer of a second conductivity type, which is a common line, and the semiconductor layer. A plurality of output semiconductor layers, which are provided as necessary and connected to an output conductor layer serving as an output line, are self-aligned along the gate electrode conductor layer and intersect with the gate electrode conductor layer. The output conductor layer, which serves as the output line, is extended on the semiconductor substrate, and information is written depending on whether or not the output semiconductor layer is formed when both the semiconductor layers are formed. A method for manufacturing an MIS type semiconductor device.