JPS584462B2 - How to use the basics - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor integrated circuit, and in particular to a method for manufacturing a semiconductor integrated circuit, in which a common semiconductor substrate is used and semiconductor oxide film isolation is used to separate each element. The present invention relates to a method of manufacturing a semiconductor integrated circuit that can reduce the area.

Semiconductor integrated circuits have enabled high-density packaging of circuit elements using planar technology and other well-known technologies, but as the complexity of the electronic computers for which they are primarily used has increased,
There is no end to the demand for higher density integration and higher speed.

When integrated circuits are formed on a common semiconductor substrate, circuit elements must be electrically isolated from each other.

As a method for this insulation, instead of the method using a reverse bias P-N junction, which has been conventionally used for convenience, a method of insulation using a semiconductor oxide film formed so as to surround the element (hereinafter referred to as oxidation The membrane separation method (referred to as membrane separation method) has dramatically advanced the above-mentioned high-density integration and speed-up.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing an integrated circuit device that achieves higher integration density and higher speed by reducing the emitter and base areas of an integrated circuit using the above-mentioned oxide film separation method.

Another object is to provide a method for manufacturing an integrated circuit device that achieves the above objects by a manufacturing method that is easier than conventional methods and also has excellent safety.

A method of manufacturing an integrated circuit using the oxidation separation method is described in detail in, for example, Japanese Patent Application Laid-Open No. 47-18284.

An example of the structure is shown in FIG. 1, which is a cross-sectional view of a bipolar integrated circuit using the oxide film separation method.

The manufacturing steps for obtaining this configuration are shown in the following numerical order.

(1) Oxidize the P-type substrate 11.

(2) Apply a mask and form N+ buried region 12 by diffusion.

(3) Remove the oxide film and grow an N-type epitaxial layer 13.

(4) Deposit and mask a silicon nitride layer (not shown).

(5) Parts of the silicon nitride layer in contact with isolation regions 14a, 14b, and 14c are removed and then oxidized.

At this time, isolation regions 14a, 14b, and 14c are all made of silicon dioxide.

(6) Region 13 to be masked and form a base region
Remove the silicon nitride layer on the surface of b.

(7) Diffuse P-type impurities to form base region 15.

Note that 16 is a silicon dioxide film formed at the same time.

(8) Remove remaining silicon nitride.

(9) Apply a mask and form collector sink region 17 and emitter region 18 by diffusion.

Note that 19 is a silicon dioxide film formed at the same time.

(10) Apply a mask and open contact windows 20a, 20
Open as b, 20c.

(11) Deposit metal for wiring, apply a mask, and perform mutual wiring as shown in 10a, 10b, and 10c.

Although the above manufacturing method has brought about significant progress in improving integration density, it still uses conventional methods for emitter diffusion and contact formation for it, so transistors are miniaturized and the emitter width is several microns ( 1~3μ
), it becomes very difficult to further open a window for contact formation in the region where the emitter is diffused.

There is a method called Washed Emitsuta to solve this problem, but it is not perfect.

The present invention uses the silicon nitride layer used to form the isolation region as a mask for diffusing the emitter region, and simultaneously uses the emitter diffusion window provided in this layer as the emitter contact formation window. The purpose is to facilitate the formation of emitter contacts and at the same time to reduce the emitter width, emitter area, and therefore base area.

Another object of the present invention is to provide a stable integrated circuit with excellent characteristics by using the silicon nitride film as a surface stabilizing and protective film for the integrated circuit.

Moreover, by forming the base region through the silicon nitride film by ion implantation, the manufacturing process can be achieved with fewer and easier manufacturing steps without increasing the number of manufacturing steps.

The manufacturing method of the present invention will be described step by step in accordance with the drawings in accordance with one embodiment.

In addition, in the figure, for convenience of explanation, the length in the depth direction is appropriately enlarged depending on the region.

First, in FIG. 2A, a silicon single crystal substrate 21 having a first conductivity type, for example, P type, is prepared, and a silicon dioxide film 22 is formed by a well-known method.

Next, as shown in FIG. 2B, a part of the silicon dioxide film 22 is removed by a well-known photo-etching technique to form an opening 23, and through this opening 23, the substrate 21 and the N-type Selectively diffuse impurities to form N+ buried region 2
4 will be provided.

Third, as shown in Figure C, the silicon dioxide film 22 in Figure B is removed, and an N-type epitaxial single crystal 25, for example, is formed on the main surface of the P-type substrate 21 by an epitaxial technique.
grow.

Fourth, as shown in Figure D, an insulator having a masking effect against the oxidizing atmosphere, typically a silicon nitride film 26, is formed.

In this case, an inclusion such as silicon dioxide may be inserted between the film 26 and the N-type epitaxial layer 25 to alleviate the strain on the epitaxial layer 25.

Subsequently, in the fifth step, as shown in FIG.
Provide c.

Therefore, the remaining silicon nitride films are separated as 26a, 26b, and 26c.

Furthermore, using these silicon nitride films 26a, 26b, and 26c as a mask, the exposed N-type epitaxial layer 25 is partially etched away and then oxidized.

The region of the epitaxial layer 25 that has been removed by etching is shown by the dotted line in the figure.

Further, 28a, 28b, and 28c are made of silicon dioxide and serve as isolation regions.

In addition, in some cases, the silicon nitride layer 2 may be removed before proceeding to the next step.
6 may be changed to an appropriate thickness by etching.

Sixth, as shown in FIG.
, 29b to cover and mask the silicon nitride films 26a and 26c.

Subsequently, P-type impurities, such as boron, are ionized, accelerated, and implanted from the main surface of the wafer.

In this case, the impurity implanted at an acceleration energy of 100 to 300 Kev and an implantation amount of 1 x 1014 to 1 x 1016/cm2 passes through the silicon nitride film and is selectively introduced into the N-type epitaxial layer 25b. P by heat treatment
A mold base region 30 is formed.

Incidentally, in the portions 26a and 26c where the resist exists, ions do not reach the epitaxial layers 25a and 25c due to a masking effect on the implanted ions.

Further, ions to be accelerated and implanted are indicated by arrows 31 in the figure.

Eighth, as shown in FIG. 2H, a portion of the silicon nitride films 26a and 26b is removed by photoetching technology,
Opening portion 32a in the area where the collector and emitter are to be formed.
, 32b are provided.

N-type impurities are selectively diffused through the openings 32a and 32b to form collector sink regions 33 and emitter regions 34.

Here, 35a and 35b are the collector sink areas 33 at the same time.
and a silicon dioxide film formed on the emitter region 34.

Next, in the ninth step, as shown in FIG. 2, a part of the silicon nitride film 26b is removed by photo-etching technique,
A window 36 is provided for contact to the base region 30.

The contact windows for the emitter and collector regions can be easily formed by removing the thin silicon dioxide films 35a and 35b with a hydrofluoric acid-based etching solution during pretreatment for the next step.

This step is extremely easy because the silicon nitride layers 26b and 26c have a masking effect on the etching solution.

Finally, as shown in FIG. 2J, wiring metal is deposited by vapor deposition or the like, and interconnections 37a
, 37b, 37c are formed.

As can be seen from the above solid manufacturing process, the present invention makes it possible to reduce the emitter area, particularly the emitter width.

This becomes clear by referring to the emitter and base patterns according to the conventional method and the method of the present invention shown in FIG.

FIG. 3A shows the conventional method, and FIG. 3B shows the method according to the present invention.

In FIG. 3A, an emitter diffusion region 39 becomes a window for an emitter contact.

Further, 40 is a window for base contact.

Others 41 and 42 are silicon dioxide films formed during base diffusion and emitter diffusion, respectively, and 43 is an isolation oxide film.

FIG. 3B shows a pattern according to the present invention, in which numeral 44 serves both as an emitter diffusion window and a contact window.

45 is a base contact window, 46 is a silicon nitride film, 4
7 is an isolation oxide film.

As transistors become smaller, the margin y for photolithographic overlay becomes x with respect to the emitter radiation X in Figure 3A.
≒y, and the area occupied by the region 42 increases when viewed from the entire transistor.

Moreover, when x and y are 1 to 2 μ, photolithography is also extremely difficult.

In FIG. 3B, since 44 serves both as an emitter diffusion window and a contact window, x can be made as small as the limit of photolithography without considering the overlap margin.

Moreover, even if the mask is slightly shifted to the left as shown by the dotted line, there is no problem because the width x only becomes narrower.

Of course, it doesn't matter if it shifts to the right.

For A, there is little room for photoengraving of subsequent contacts.

As described above, in the present invention, the emitter width can be reduced using a simpler technique, and the characteristics at high frequencies can be improved.

Furthermore, the area of the transistor becomes relatively small, and the degree of integration increases.

Comparing the entire process, the conventional method described above (6),
The step (8) of removing the silicon nitride layer is no longer necessary and is simplified.

The number of photolithography steps is the same, but photoetching of the contacts is made easier by only opening the base contact window.

Furthermore, since the surface of the circuit element is covered with a silicon nitride film, the stability of the element is superior to the conventional method in which the surface is protected with a silicon dioxide film.

As is clear from the above, according to the manufacturing method of the present invention, integrated circuits with excellent high frequency characteristics and stability can be manufactured with high density and more easily than with conventional methods.

[Brief explanation of the drawing]

FIG. 1 is a partially cutaway cross-sectional view of a conventional integrated circuit device, and FIGS. 2A-2 are partially cutaway cross-sectional views showing a manufacturing method according to an embodiment of the present invention in the order of steps. Further, FIGS. 3A and 3B are enlarged plan views of the pace emitter portion according to the conventional method and the method of the present invention, respectively. In the figure, 21 is a P-type substrate, 22 is a silicon dioxide film, 2
3 is an N+ buried region diffusion window, 24 is an N+ buried region, 25
are N-type epitaxial layers, 26, 26a, 26b, 26
c is a silicon nitride film layer, 27 is a window for forming an isolation region, 28 is an isolation region (silicon dioxide film), 29 is an ion blocking resist, 30 is a base region, 31 is an ion beam, 32
a is a window for forming an N+ collector sink region, 32b is a window for forming an emitter region, 33 is a N+ collector sink region, 34
35a and 35b are silicon dioxide films formed during diffusion of the N+ region, 36 is a window for forming a base contact, and 37a, 37b, and 37c are metals for wiring.

Claims (1)

[Claims] 1. A semiconductor epitaxial layer is provided on the surface of a semiconductor substrate, an insulating layer of a silicon nitride film is provided on the epitaxial layer, this insulating layer is patterned, and the epitaxial layer is selectively oxidized using the insulating layer as a mask. Change to insulator,
a step of forming a plurality of electrically insulated island-shaped semiconductor epitaxial layers, a step of forming a base region by ion implantation while leaving the insulating layer used as a mask during the selective oxidation, and a step of forming a base region in the insulating layer. A method of manufacturing an integrated circuit device comprising the steps of: opening a window for emitter diffusion; and etching away a silicon dioxide film formed within the window after the emitter diffusion.