JPS5845185B2 - Connection method between diffusion layer and wiring layer in integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit device with improved connection method between a diffusion layer and a wiring layer.

With the development of manufacturing technology for semiconductor devices, the industry related to integrated circuits has also expanded.
O8-type LSIs (Large-Scale Integrated Circuits) are now on the market as products.

In a silicon gate 1-M0 S type LSI, the area of the gate part is reduced to half underground compared to an aluminum gate, or the wiring part is not very small.

This is because when making contact 3 between the diffusion layer 1 and the aluminum wiring layer 2 as shown in FIG. 1, the diffusion layer 1 is
This is because it is normal to design the contact hole 4 with a size such that the contact hole 4 does not come out of the diffusion layer 1 even if the mask is shifted inside the contact hole 11J by increasing the size of the contact hole 4.

Considering this contact 1 ~ hole, the wiring pin a
The force 3 is 15 times that of the case where no contact hole is provided, which has a serious effect on the chimp size, and has disadvantages such as the pattern arrangement being disturbed and the pattern design becoming complicated.

Therefore, an object of the present invention is to maintain contact between the diffusion layer and the wiring layer without changing the arrangement pitch of the diffusion layer formed on the surface side of the substrate, and to maintain it at the minimum pinch. An object of the present invention is to provide a semiconductor integrated circuit device with improved connection between a diffusion layer and a wiring layer.

An embodiment of the present invention will be described below with reference to FIGS. 2 and 3.

In the figure, reference numeral 11 denotes a semiconductor substrate on which a large number of semiconductor elements such as MO8 type field effect transistors are provided. On the surface of this substrate 11, a large number of diffusion layers 12 are formed after passing through an oxide film (Si02) 13 coating step 2 selective etching step. Installed in parallel.

The pinch a' between these diffusion layers 12 is maintained at the minimum pinch (for example, 16 μ) that does not allow for mask displacement.

Next, a hole 14 is provided to the contact 1 in the oxide film 13 on the diffusion layer 12 to be contacted (in this case, the diffusion layer located on the left side), and a semiconductor block is directly contacted with the diffusion layer 12 through this contact hole 14. (
A description will be given below using a polycrystalline silicon layer as an example.

) 15 are stacked. This polycrystalline silicon layer 15 has a pattern shape in which the portion exposed to the surface from the oxide film 13 is sufficiently wide in consideration of mask displacement in a subsequent process.

Next, an oxide film 1 is placed on the polycrystalline silicon layer 15 and the oxide film 13.
6, contacts 1 to holes 17 are provided in the oxide film 16, and an aluminum wiring layer 18 connected to the polycrystalline silicon layer 15 through the contact holes 17 is laminated.

In order to provide the above-mentioned patterned polycrystalline silicon layer 15 and aluminum wiring layer 18, the coating process of these layers and -1-
This may be done by a notching process.

As described above, the polycrystalline silicon layer 15 is used as an intermediary for contact between the diffusion layer 12 and the aluminum wiring layer 18, and the polycrystalline silicon layer 15 located in the middle is widened sufficiently, that is, by an amount that allows for mask displacement. In addition, the arrangement pitch between each diffusion layer 12 can be changed, and the contact between the diffusion layer 12 and the aluminum wiring layer 18 can be made with the minimum necessary width without increasing the width of the diffusion layer 12 at the contact portion. It is.

In the above embodiment, aluminum was used as the upper wiring layer for contact 1-, and polycrystalline silicon was used as the conductive layer used as an intermediary for the contact, but two-layer wiring made of one of these materials may also be used. , and other conductive materials may also be used.

Further, the term "diffusion layer" as used in the present invention has a broad meaning including a layer formed by ion implantation.

As explained above, according to the present invention, contact is made between the diffusion layer and the wiring layer using the conductive layer as an intermediary, so there is no need to widen the width of the diffusion layer in a part of the contact 1, and the wiring It is possible to provide a semiconductor integrated circuit device in which the connection between the diffusion layer and the wiring layer is improved without disturbing the pinch.

[Brief explanation of the drawing]

Fig. 1 is a pattern diagram for explaining the connection method between diffusion layers and wiring layers in a conventional integrated circuit, Fig. 2 is a pattern diagram for explaining an embodiment of the present invention, and Fig. 3 is a pattern diagram for explaining the connection method between diffusion layers and wiring layers in a conventional integrated circuit. FIG. 3 is a sectional view of a contact portion. 11...Semiconductor substrate, 12...Diffusion layer, 13°16...Oxide film, 14,1γ...
...Contact hole 18...Aluminum wiring layer.

Claims (1)

[Claims] A semiconductor substrate of a 1-4 conductivity type, a plurality of parallel diffusion wirings of other conductivity types provided on the semiconductor substrate, and a semiconductor substrate formed on the semiconductor substrate. In an integrated circuit having an insulating film and an electrode wiring formed on the insulating film, the electrical connection between the diffusion wiring and the electrode wiring made at any location is: - the diffusion wiring and the diffusion wiring; A semiconductor block is formed between the pinches formed by the diffusion electrode, and the die reflex I/contact I is formed between the holes for direct contact and the electrode wiring is contacted to the semiconductor block. The semiconductor integrated circuit device is characterized in that a portion of the semiconductor block on the side connected to the electrode wiring is made wider than a portion of the semiconductor block on the side connected to the diffusion wiring. . 2. A semiconductor integrated circuit device according to claim 1, wherein the electrode wiring runs in a direction crossing the diffusion wiring. 3. The semiconductor integrated circuit device according to claim 1, wherein the electrode arrangement is aluminum electrodes and the semiconductor block is polysilicon.