JPS5845202B2 - Gijisei Genha Hatsusei Cairo - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a circuit that has a simple circuit configuration and generates a pseudo sine wave output with few harmonic components based on digitally displayed phase information.

Strings have traditionally been digital phase locked loops (
Digital Phase Locked Loo
p ) digital VCO (Voltage Co
The SI N-ROM (Read 0nly Memory
y ) is commonly used.

Furthermore, for high-speed requirements where read time becomes an issue, a triangular wave generating circuit is used instead of the SlN-ROM.

This circuit can be expected to have a shorter cycle time than the former, and its harmonic components are not so large.

However, in this circuit as well, when considering the multiplication of the triangular wave and any other arbitrary waveform by the phase comparator, it takes about the same amount of time as the former.

Furthermore, in order to further shorten this multiplication time, there is a method of using a square wave of ±1 instead of a sine wave or a triangular wave and performing multiplication with another binary number display signal wave by puncturing the exclusive OR circuit. It is considered.

In this case, many of the harmonic components of the square wave will be included in the multiplication result, and since the system is sample value control, higher harmonics will also fall into the band due to folding, so only the harmonic components will be included in the multiplication result. It cannot be made smaller.

The purpose of this invention is to solve the above-mentioned contradictions.
The object of the present invention is to provide a pseudo sine wave generator which has a simple configuration, has few harmonic components, and has a short cycle time for multiplication when considering multiplication with other signal waveforms.

Next, the configuration and principle of this invention will be explained.

First, (II) = (11, I2.I3.I,, -...-I
n) However, n: Integer I 1: MSD (Most 51gn1fican
t Digit)In: LSD(Least 5
For the binary code input displayed as 1gn1ficant digit), the same binary code output (S, Q) ) = (s, o,, o□, 03...
・(M).

Considering (1<#<n-2) and let ni and llj be any two inputs of (n), the outputs (S, 0) (Q)) for each are (C))i, (Q) )j, if I2-O, (II)i>(IIN, then (0)i≧(O)”...
・・・・・・・・・(1) If I2-1 (If)i>(II)j then (0)i≦(Q))j
(■) and 5=11 (It is the negation of ■1□) that satisfy the following relationship and do not include two or more 1s in the code example are 2 A logic circuit having a base number code output (S, O)) is provided.

Such a logic circuit will be shown later in Example 1, but
Physical realization is possible with a combination of basic logic elements.

Furthermore, an accumulator consisting of a flip-flop circuit, a memory circuit array, etc., which can accumulate binary code input at a constant period and display and output the accumulated value in binary code (I). By connecting the output terminal of the accumulator and the input terminal of the logic circuit, the output 1 (S, Q)) of the logic circuit increases the sine wave amplitude by +1. ±7・±I2・+−
! -3. . . . A pseudo-2 quasi-sine wave generation circuit representing a waveform quantized to a value of 0 is constructed.

(The amplitude is normalized by the maximum amplitude.

From now on, we will normalize it.

) Now, let θD be the value of (I) and the phase whose maximum value corresponds to 2π, then I2-O is O≦θD≦.

Indicates the state of π≦θD≦100π and represents the absolute value of the amplitude (0
) is monotonically increasing under the restriction of equation (1) in this state,
12=1 indicates the state of 1≦θD≦π°7 and 2π≦θD≦2π, and according to the restriction of equation 2), it is monotonically decreasing in this state.

Furthermore, due to the condition that (0) does not include two or more 1's, the value of (Q) cannot be anything other than 2-.

(Here, k is a non-negative integer.

) Also, 11-0 indicates the state of O≦θD≦π, and in this case S=
1, and 11=1 indicates a state of π≦θD≦2π, and in this case, it becomes S-0, and the sign output S of 1 corresponds to positive and O corresponds to negative.

Therefore, the output (S,0) becomes a pseudo iE sine wave binary representation output obtained by quantizing the sine wave with a value of 2-.

Specific embodiments of the present invention based on the basic principles of the configuration and operation described above will be described with reference to the drawings.

FIG. 1 shows an embodiment of the present invention. Clock source 3
The logic circuit 2 is an accumulator 1 that accumulates an arbitrary value added to the input terminal 101 at the input terminal period.
Human power ~ connected.

This logic circuit becomes (S,
This figure shows the case where n = 5 in a logic circuit whose output is (2).

Figure 2 shows this logic circuit (n) = (11, I2゜I3
．． I4. Output (S, 0) when input of I5) is received =
(S, 01, 02, 03).

FIG. 3 shows an embodiment of the logic circuit 2 shown in FIG.
．． I5) are applied in parallel.

13 is a binary inverter, which takes out an output S representing the sign from 11 which is the MSD of the input of 103.

11 and 11' are binary AND circuits, and 14 and 14'. 1
4'1 is a binary NOT circuit, and 12.12' is an exclusive OR circuit, which generates outputs 01, 0□, and 03, which are sent to the output terminal 102 together with S.

Now, returning to FIG. 1, we will consider the operation over time.

A constant input of 1 is fixed to the input terminal 101 and is added to an accumulator of 1 for each clock.

FIG. 4 shows the temporal change of the output terminal 102 at this time.

In both FIGS. 4A and 4B, the horizontal axis shows time, and the vertical axis shows the output value of the logic circuit 2 in a and the content of the accumulator 1, that is, the value at the terminal 103 in b.

When a constant value is accumulated in the accumulator at a constant period, it is obtained from the pseudo sine wave output terminal 102 of a constant frequency, as can be seen from the correspondence of values shown in FIG.

From a in the same figure, this output waveform is −〉θ〉−! -(7!-).

2 2 2 1 π 1 π 1 π2 (100)
〉θ≧1 (ヲ), 7 (100)〉〉θ≧0, it is found that the values are , 1 1-, 2'4, respectively, and the harmonic components included in this waveform are equivalent to those of a triangular wave. Or have fewer characteristics.

Generally, by allowing an arbitrary input value to the input terminal 101 for each clock, the frequency of the pseudo sine wave output from the output terminal 102 can be changed.

On the other hand, if the input to the input terminal 101 is kept constant and the output of the clock generation source 3 is gated using control information,
Similarly, the output wave frequency of the output terminal 102 changes.

In other words, this control method corresponds to adding zero and non-zero constants to the input terminal 101 for each clock according to control information.

Therefore, the structure and operation of the accumulator, which is operated by the clock gated with control information, accumulates a certain constant every time the clock is gated, and applies the output to the input terminal 103 of the logic circuit 2. This is naturally included in the embodiment of FIG. 1 in which the accumulator output, whose values are accumulated, is applied to the input terminal 103 of the logic circuit 2.

Next, a few application examples of the pseudo sine wave generating circuit according to the present invention will be shown.

(1) Application of arbitrary time function and sine wave to digital multiplier FIG. 5 shows a schematic diagram of the configuration of one applied embodiment.

First, in order to create a pseudo sine wave, a certain constant is applied to the accumulator 1 from the signal generator T at a certain period.

The continuous waveform shown in FIG. 4 is output from the logic circuit No. 2.

A shift register 5 shifts the output of the AD converter 4 by the output (O) from 2.

In other words, (0)k←(Q)) When (0)k=1, the bits are shifted by (4-1).

((O)) has only one 1 in its output.

) Ok=1 represents the pseudo sine wave amplitude 2-(distortion -1), so by this shift, the binary display input is multiplied by this pseudo sine wave.

However, since the S output of the logic circuit 2, that is, the sign, is not related, it is multiplied by its absolute value.

Then, the sign converter 6 signs the value of the output of the shift register 5 using the S output, and the operation is completed, and the result of the multiplication is sent to the output terminal 107.

The above operation l Thus, the arbitrary time function applied to the input terminal 106 is multiplied by a sine wave of an arbitrary frequency.In this way, the multiplication is accomplished by a single shift operation, and the harmonic distortion is also small. is obtained.

A multiplier is constructed.

(2) Digital Phase Locked
APPLICATION TO LOOP FIG. 6 shows a schematic diagram of the configuration of the next applied embodiment.

Adder 15 adds the constant obtained from signal generator 7 and the output of multiplier phase detector 10 to
The block 9 surrounded by a dotted line constitutes a digital vCO.

The multiplicative phase detector 10 is comprised only of a shift register 5 and a code converter 6.

The time function having phase information is connected to 108 input terminals and converted into a value expressed in binary by four A, D converters.

8 is a filter.

By adopting the configuration shown in FIG. 6, the cycle time of the system is shortened, and harmonic noise due to the approximation of a sine wave in the output from the system is small compared to other approximation methods.

(3) For SIN-ROM type square wave sinusoidal wave generation circuit, FIG. 7 is a schematic diagram of still another applied embodiment of the present invention.

This can be recalled from the description of the basic principle mentioned earlier,
By passing the output of the logic circuit 2 through the filter 8, a sine wave with a certain degree of accuracy can be obtained with a simple configuration.

That is, when the amount of phase change between clock cycles is applied to the input terminal 109, a sine wave of a frequency corresponding to the amount of phase change is applied to the output terminal 110.

The principle, one embodiment, and three applied examples of a circuit for obtaining a pseudo sine wave with few harmonic components by adding an arbitrary amount of phase change at a constant period have been described above.

According to the present invention, as described in the application examples, it is possible to multiply an arbitrary signal wave represented by a binary code by a sine wave very easily and with low deterioration. Needless to say, it is important in digital signal processing circuits for carrier waves and their application devices.

In addition, in Fig. 3, (n) = (II, I2''
・Although we have shown an example using a logic circuit that outputs (S, q)) of equation 3) for an input of In), the configuration of the logic circuit is not limited to equation (3) and )=(11
゜I2. I3. If I2-0 for the input (I, , -In), (II)i>(II)j, then (■)i≧(■)jI
In the case of 2-1, if (II) i> (II)j, then (Q))i≦
This also applies when using another logic circuit that satisfies the relationship (0)j and has an output (S, Q) consisting of (0) and 5=11 without two or more 1s in its code string. It is not beyond the realm of invention.

Further, regarding application examples, although typical application examples have been described, it goes without saying that the present invention is not limited to these.

[Brief Description of the Drawings] Figure 1 shows an embodiment of the present invention, in which 1 is an accumulator, 2 is a logic circuit, 3 is a clock generation source, 101 is an input terminal to the accumulator, and 102 is a logic circuit. 2 output terminals are shown respectively. Figure 2 shows the input characteristics of the logic circuit that is its component, and the third
The figure shows one embodiment of the logic circuit, and FIG. 4 is a characteristic diagram for explaining the operation of the embodiment shown in FIG. 1. FIG. 5, FIG. 6, and FIG. 7 each show a schematic diagram of the configuration of an applied embodiment of the present invention.

Claims (1)

[Claims] 1 (it)=(It, I2.I3.I, ”-”I
n) However, n: Integer I 1: MSD (Most 51gn1ficant
Digit)In: LSD(Least 51gn)
1f 1cant Digit'. Similarly, the binary code output (S r O) ""' (S r 01 + 02 +
03...(M). Considering (1≦l≦n-2), let any two inputs of (I) be (If)i, (If)j, and the outputs (S,
Let the (0) of 0) be (0)i and (0)j, and if l2=O, (II)i>(II)j, then (0)i≧(0)j■2
= 1, if (I)i>(II)j, then the relationship (0)iζ(0)j is satisfied, and (0) and 5=11 such that the code string does not have two or more 1s. includes a logic circuit that outputs binary code (S, O), and an accumulator that accumulates arbitrary input values in a fixed period and displays the accumulated value in binary code (II). A pseudo sine wave generation circuit, characterized in that an accumulated signal output terminal of a simulator is connected to an input terminal of the logic circuit, and an output (S, O) of the logic circuit is taken out from the output terminal.