JPS5845221B2 - Time division character multiplex transmission equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a time-division character multiplex transmission device used for exchanging information between a plurality of low-speed lines and one high-speed line.

Lines used for data communication have various speeds, but in general, high-speed lines have a low transmission cost per unit amount of information.

Therefore, when a large number of low-speed lines are required between two remote points, the low-speed lines are multiplexed with some kind of device, and one
It is more advantageous to transmit over two high-speed lines.

One of the devices that achieves this purpose is a time division character multiplex transmission device.

Furthermore, there are various types of low-speed lines, each requiring specific control.

For example, in a telephone-quality line that does not allow simultaneous transmission in both directions, it is necessary to control the carrier, and in a switched line, it is necessary to control connection and disconnection of the line.

Furthermore, in telephone quality lines, control called polarity reversal or break signals may be performed.

Therefore, when information from these various lines is multiplexed, it is necessary to transmit control information that indicates the status of the line in addition to characters that alert the transmitted and received data.

However, conventionally proposed time-division character multiplexing transmission apparatuses have the drawback of not being able to transmit such control information.

SUMMARY OF THE INVENTION An object of the present invention is to provide a time division character multiplexing transmission device that can easily exchange control information on various lines.

In the present invention, transmission of control information on a low-speed line may involve some delay, and when transmitting control information, it is not necessary to transmit characters. A time division character multiplexing transmission device is obtained which is configured to transmit control information when the control information is not available.

According to the present invention, there is provided a time division character multiplex transmission device installed at both ends of a high speed line for exchanging information between a plurality of low speed line modems or communication control devices and the high speed line. An interface control signal with a modem of a low-speed line or the communication control device and a means for converting the control signal of the low-speed line into control information, and when there is no character to be sent to the other end of the high-speed line, the control signal is transmitted via the high-speed line. means for transmitting the converted control information instead of the character; and means for distinguishing between the control information and the character sent from the other end of the high-speed line;
A time division character multiplexing transmission device is obtained which includes means for converting control information among the transmitted information into an interface control signal for a low-speed line modem or communication control device and a low-speed line control signal.

Regarding the interface control signal with the modem or communication control device, the terms used in the interface between the JIS-C-6361-1971 modem and the communication control device and data terminal device are used.

The present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing a data communication system using the time division character multiplex transmission apparatus of the present invention.

Referring to FIG. 1, n data terminal devices 11 to 1n
are low-speed lines 1-n corresponding to each terminal device and modems 21-2n and 31-n provided at both ends of each low-speed line 1-n.
3n, the time division character multiplex transmission device 40 (
(hereinafter referred to as MPX(A) 40).

Furthermore, the MPX(A) 40 is connected to a time division character multiplexing transmission device 50 (hereinafter referred to as MPX(B) 50) provided at the other end through a modem 41, a high-speed line 42, and a modem 43.
and exchange information.

Furthermore, the MPX(B) 50 is a communication control device 60 (hereinafter CC).
The central processing unit 70 (hereinafter referred to as CPU
70).

As shown in Figure 1, MPX (A) 40
Since it is directly connected to modems 31 to 3n of ~n, it is called a modem direct connection type. MPX (B) 50 is directly connected to CCE 60 and looks like a modem from CCE 60, so
I will call it the modeto simulation type.

MPX(A) of the present invention provided at both ends of the high-speed line 42
40 and MPX(B) 50 not only multiplex characters, but also interface control signals with modems 31 to 3n of low speed lines 1 to n or CCE60 and low speed line 1.
- n control signals to the high-speed line 42 to be converted into control information and transmitted, and a function to distinguish between characters and control information.

Figures 2a and 2b are diagrams for explaining the structure of information in a high-speed line. Figure 2a shows the frame structure in the high-speed line, and Figure 2 shows the structure of each subframe that makes up the frame. ing.

Referring to FIG. 2a, the number n of multiplexed low-speed lines is 7, and the high-speed line is 2400 bits/sec.

In this case, a low-speed line 1 of 1200 bits/second and a 200 bit/s
It is multiplexed with low-speed lines 2 to 7 of bits per second.

When such information is multiplexed, one frame consists of 12 subframes, and each subframe consists of 10 bits.

Therefore, one frame consists of 120 bits of information.

The numbers in FIG. 2a indicate the assigned line numbers, and it can be seen that each subframe is priced according to the transmission speed.

Referring to Figure 2, each subframe consists of 10 bits, one of which is designated as the frame synchronization bit F.
, S, and the other bits are modification bits M and S.

These modification bits M and S indicate that the following 8 bits of information are 1
This bit indicates whether it is a character or control information.

In the following explanation, one character or 8 bits of control information will be simply referred to as data.

FIG. 3 shows a time division character multiplex transmission device (MP) of the present invention.
It is a block diagram showing one example of X).

This MPX has one high-speed line controller (HST, C)
300, and low-speed line control units (LSLC) 301 to 30n installed for the number n of low-speed lines.

Each LSLC 301 to 30n has a function of assembling characters sent from a low-speed line and a function of creating control information sent to a high-speed line.

Now, for LSLC301~30n, H8LC300
When a data transmission request signal is applied from signal lines 81 to Sn, the LSLCs 301 to 30n transmit the character if there is a character to be transmitted, or transmit control information if there is no character through the input data buses IB1 to IBn. Send each to H8LC300.

At the same time, LSLC301~30n sends a modification bit indicating whether the data sent to input data bus ■B1~IBn is a character or control information to H8LC300 via input modification bit line ■M1~IMn. .

On the other hand, when the H8T, C300 sends a data acquisition request signal to the signal lines R1 to Rn, the LSLCs 301 to 30n output data buses OB1 to OBn in response to this acquisition request.
Takes data given from.

At the same time, it receives the modification bits sent via the output modification bit lines OM1 to OMn, and depending on the state of the modification bits, it is determined whether the received data is a character or control information.

If the received data is a character, it is disassembled and sent to a low-speed line, and if it is control information, control is performed according to the control information.

When the H8LC300 sends a data transmission request signal to the signal lines S1 to Sn, it sequentially scans the LSLCs 301 to 30n according to the order shown in FIG.
Receives data from input data buses 1 to 30n through input data buses B1 to IBn, and input modification bit lines IM1 to IM
Receive modification bits via n.

Furthermore, in the H8LC, a frame synchronization bit is added to the data and modification bits received from the LSLCs 301 to 30n to form a subframe, and the subframe is sent to the high-speed line while maintaining frame synchronization.

On the other hand, when the H8LC 300 receives information from a high-speed line, it first detects frame synchronization and decomposes it into subframes.

Next, the frame synchronization bit is removed, and the data is sequentially sent to the LSLCs 301 to 30n via the output data buses OB1 to OBn according to the order shown in FIG. - output data, and output modification bits via output modification bit lines OM1 to OMn.

Figure 4 shows the low-speed line control section (LSL) of a modem-directly connected MPX.
It is a figure showing an example of - composition of C).

Referring to FIG. 4, the modem direct-connection type MPX has a control circuit 400 that controls each part, a control information circuit 401 that sends and receives status control information, and a character assembly circuit 402 as a transfer system from the modem to the H8LC. , a reception character buffer 403 and a multiplexer circuit 404.

Furthermore, a transmission character buffer 405 and a character decomposition circuit 406 are provided as a transfer system from the H8LC to the modem.

Now, the case of transferring information to H8LC will be explained.

When control signals such as DR, CD, C8, CI, etc. are given to the control information circuit 401 from the modem, the control information circuit 401
creates state control information.

On the other hand, the received data RD from the modem is given to a character assembling circuit 402, and after assembling characters in this circuit, it is held in a received character buffer 403.

In this state, when a data transmission request is given to the signal line S from the H8LC, if there is a character in the receive character buffer 403, the contents of the receive character buffer 403 are selected in the multiplexer circuit 404 under the control of the control circuit 400, and input Transfer to H8LC via data bus IB.

If there is no character in the received character buffer 403, the control information created by the control information circuit 401 is selected by the multiplexer circuit 404 and sent out.

Simultaneously with the transfer of these data, the control circuit 400 creates an input modification bit based on the contents of the data, and transmits it to the H8LC via the input modification bit line IM.

On the other hand, when transmitting information to the modem, first, the control circuit 400 receives a data acquisition request sent from the H8LC via the signal line R.

Next, the control circuit 400 stores the data sent through the output data bus OB in the transmission character buffer 405 or the control information circuit 401 according to the output modification bit sent to the output modification bit line OM.

If the data sent from the H8LC is a character, the data is sent to the character decomposition circuit 406 via the transmission character buffer 405 and decomposed into characters. The signal is sent to the modem via the signal line SD.

Further, when the data is control information, the control information circuit 4
At step 01, the signal is converted into control signals ER, R8, etc. to the modem, and then sent to the modem.

FIG. 5 is a block diagram showing an example of the configuration of a low-speed line control device LSLC in a modem simulating type MPX.
In SLC, communication control device CCE and high-speed line control device H8
Transfers information to and from the LC.

Referring to FIG. 5, it has a control circuit 500 and a control information circuit 501, as in the case of FIG.
Character assembly circuit 502 as an information transfer system to 8LC
and a reception character buffer 503, and a transmission character buffer 505 and a character decomposition circuit 506 as an information transfer system from the H8LC to the CCE.

In this embodiment, the control signals ER, R8, etc. are given to the control information circuit 501 from the CCE, and the control signals ER, R8, etc.
From 01, control signals DR, CD, C8,
CI etc. are sent.

Further, transmission data from the CCE is sent to the character assembly circuit 502 via the signal line SD, and reception data to the CCE is sent from the character disassembly circuit 506 via the signal line RD.

Since the other points are the same as in the case of FIG. 5, the explanation will be omitted here.

FIG. 6 is a diagram for explaining polarity reversal operation in a telegraph quality line.

In this example, when there is no transmission character CH, the line is held in the A state, and when there is a transmission character CH, the line is reversed from the A state to the Z state, then the character is transferred, and when the transmission is completed, the line is changed from the Z state. Reversal to state A.

Character transmission can only be performed after the Z state continues for a certain period of time.

FIG. 7 is a block diagram showing an example of the configuration of an MPX control information circuit used in a telegraph quality line.

The flip-flop 701 is a circuit for storing input control information IC, and this flip-flop 701 is set when the differentiating circuit 702 detects that the received data RD has changed from the A-state to the Z-state. Ru.

Further, when the resettable timer 703 detects that the A state has continued for a certain period of time, the flip-flop 701 is reset by this output.

This fixed time must be long enough that no output is generated due to the transmission character, but it must be short enough that the difference in the duration of the Z state between before and after transmission over the high-speed line is small due to transmission delays. It won't happen.

Therefore, a transmission time of about 10 bits over a low-speed line is appropriate.

Incidentally, the received data R and D are given to a differentiating circuit 702 and also sent to a character assembly circuit CH.

Flip-flop 710 is a circuit for storing output control information OC, and a gate 711 performs an AND operation between this output and output DO from the character decomposition circuit, and sends out the result as transmission data SD.

Thus, when flip-flop 710 is turned on, the content of the character is sent while the character's field action is being performed.

Furthermore, when the character disassembly operation is not being executed, the Z state is maintained, and when the flip-flop 710 is off, the A state is maintained.

This flip-flop 710 is connected to a gate 71 where the output control signal OC and the character output signal CHO are logically summed.
2 and reset by a signal from NOT gate 713.

However, since the transmission of characters takes priority over the transmission of control information, the transmission of control information may be delayed.

Also, since the character is not transmitted in the Z state,
When a character is transmitted, this flip-flop 710 is set through an OR gate 712.

As described above, since the present invention transmits control information when there is no need to transmit characters, it can be easily applied to many types of line systems.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an embodiment of a data communication system using the present invention, FIG. 2a is a diagram showing a frame structure of a high-speed line, and FIG. FIG. 3 is a block diagram of a time-division character multiplexing transmission device showing an embodiment of the present invention, FIG. 4 is a diagram showing the configuration of a modem direct connection type low-speed line control section, and FIG. 5 is a modem simulation type low-speed line control section. Figure 6 is a diagram showing the configuration of the line control unit, Figure 6 is a diagram showing an example of polarity reversal operation of a telecommunications quality line, and Figure 7 is a diagram showing the state control information circuit of a time-division character multiplexing transmission device used for telecommunications quality lines. FIG. 3 is a diagram showing the configuration. Explanation of symbols, Figure 1, 1-n...Low speed line, 11-1
n-data terminal device, 21-2n, 31-3n...
・Modem, 40.50... Time division character multiplex transmission equipment (MPX), 41, 43... Modem, 42...
High-speed line, 60...Communication control equipment (CCE), 70...
・Central processing unit (CPU), Fig. 3, 301-30n
”・Low-speed line control unit (LSLC), 300...High-speed line control unit (H8LC), Figures 4 and 5, 400,5
00...Control circuit, 401.501...Control information circuit, 402,502...Character assembly circuit, 403
．． 503... Receive character buffer, 404, 50
4... Multiplexer circuit, 405.505... Transmission character buffer, 406.506... Character decomposition circuit.

Claims (1)

[Claims] 1. In a time-division character multiplexing transmission device installed at both ends of a high-speed line for exchanging information between a plurality of low-speed line modems or communication control devices and the high-speed circuit, the low-speed line or communication control device a first buffer that converts and holds an interface control signal for the low-speed line and a control signal for the low-speed line into control information; a second buffer that holds characters to be sent to the other end of the high-speed line;
The state of data storage in the second buffer is detected, and when data is stored, the contents of the second buffer are sent to the other end of the high-speed line, and when no data is stored, the contents of the first buffer are sent. means for transmitting content to the other end of the high-speed line; means for distinguishing data received from the other end of the high-speed line into control information and characters;
detecting the third and fourth buffers that hold the received control information and characters and the state of data storage in the fourth buffer, and when data is stored;
means for transmitting the contents of the fourth buffer to the modem or communication control device and transmitting the contents of the third buffer to the modem or communication control device when no data is stored; A time-division character multiplexing transmission apparatus, comprising means for converting the content into an interface control signal for the modem or communication control device of the low-speed line and a control signal for the low-speed line.