JPS5845714B2 - video heart warmer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to data processing apparatus and, more particularly, to digital television display systems.

Conventional digital television (hereinafter abbreviated as DTV)
Display systems generated line drawings by storing one video bit for each pixel.

In many such traditional systems, raster
An assembly storage device would have to store as many as 1 million video bits for a 1024×1024 raster matrix, for example.

The complete picture is then transferred to refresh storage.

One significant drawback of such conventional display systems is that when changing the displayed image, either a new image must be generated or the entire million bits must be sent to raster assembly storage for modification. What is necessary is the action of returning it again.

Therefore, erasing a single vector once requires either reconstruction of the entire raster or transfer of all 1 million bits from storage for modification and replacement.

If two vectors intersect each other, the process of erasing the first vector, after returning it to assembly storage, removes the video bits common to both vectors, so that the remaining vector, i.e. A gap is formed in the vector that separates the components on either side of the erased vector.

Advances have been made in the past through the use of queue memories for storage of digitally encoded video data.

For example, one such conventional system uses a video generator with a refresh buffer to display data.

The use of such buffers allows the size of raster assembly storage to be smaller than previously possible.

However, this image buffer must be large enough to handle the tallest characters to be displayed.

It has been found that this requires at least eight rask lines, all of which must be stored in the video image buffer.

If a vector exceeds the vertical height of such a video image buffer, the vector must be generated as separate, separate segments.

This changes the contents of the vector registers within the vector generator so that the vector generator can continue operating again later in the scan sequence.
This is accomplished by returning to a threaded list of buffers.

Obviously, by accessing the concatenated buffer itself, accessing the next component of the vector in the next set of raster lines to be scanned requires considerable processing and thus reduces the display power of the system. However, the complexity will also increase.

What is desired in the art is a streamlined means of efficiently accessing subsequent components of vectors and other data stored in the system for display at a faster rate.

It is an object of the present invention to store graphical and alphanumeric display data in such a way that it can be accessed more efficiently than conventional methods.

Another object of the present invention is to store graphical display data in such a way as to preserve its identifying and special attributes, such as color, intensity or brightness (bl 1nk).

Another object of the invention is to display decomposed figures as vector segments in an improved manner.

Another object of the invention is to store graphical display words such that graphical display words loaded in an irregular order are sorted into a linked queue of sequential raster line positions.

Another object of the invention is to circularly store continuous data that is continuously modified as raster fields occur.

Dynamic DTV display technology can be generally described as follows.

DTV is a display technology that receives encoded data from a computer and converts it into a TV video signal.

This signal drives one or more TV monitors that present the desired computer display graphics.

The logic for converting encoded computer data into TV signals is all digital logic, the same as that used in conventional computers.

Accordingly, DTV has successfully incorporated technological advances in both the television and television industries to provide unique computer display capabilities.

A TV display in the sense used here is a system in which a beam of electrons (one for each primary color) is passed across the screen of a cathode ray tube in a series of closely spaced parallel lines (called a raster). It is of the type that is repeatedly deflected.

This is repeated a fixed number of times per second (refresh rate).

Within a particular display system, the number of parallel lines and refresh rate are generally constant.

A typical display system has 525 lines and is refreshed 30 times per second.

Each frame is divided into two fields.

One field consists of odd numbered rask lines and the other field consists of even numbered rask lines.

As a result, interlaced scanning, which apparently doubles the refresh rate, is performed.

DTV provides a computer display in TV format by decomposing an image into a matrix of points or display elements.

In a rask line display, the number of vertical display elements is equal to the number of visible Lanuta lines.

The number of display elements within each raster line is somewhat arbitrary, but is chosen to be 1.33 times the number of raster lines.

This follows the 4:3 aspect ratio of a TV cathode ray tube.

Even if an image is made up of elements, there are so many elements used that the image appears continuous.

The present invention provides an on-the-fly
)” or “implicitaef
It utilizes a new graphic generation technique known as "Resh".

This is in contrast to "explicitrefresh" in previous DTV systems.

On-the-fly technology allows the identity of all displayable data to be preserved in encoded form until the final stage of video generation.

Implicit refresh allows certain data to be erased without erasing overlapping (intersecting) data, thus allowing selective modification of data.

This display generation method is particularly preferred when flashing and color are desired.

Attribute bits for color and flash identification are stored in computer encoded form.

In terms of hardware, implicit refresh can reduce storage requirements for color graphics displays by a factor of 18.

The present invention relates to a video generation circuit for converting an irregularly occurring data signal representing a graphical pattern into a time-sequential video signal for use in a sequential line-scanned display device, This can be used, for example, in a DTV system as described above.

A video generation circuit according to the present invention includes an associated refresh buffer that receives a data signal and sorts it into one or more groups based on extreme raster line positions for a display pattern, and an output of the refresh buffer. having a first input connected to the display, storing the ordered data signal from the refresh buffer once for each display field before displaying the pattern, and synchronizing the ordered data signal with the line scanning of the display. an intermediate buffer that outputs an output signal, and an intermediate buffer that is connected to the output of the intermediate buffer and decodes the ordered data signal output from the intermediate buffer.
a graphic pattern generator that generates a component on a raster line to be scanned of the display pattern to a first output line; and a raster line that is connected to the first output line of the graphic pattern generator and is to be scanned of the display pattern. and a partial raster assembly store for storing the components in the line.

A graphical pattern generator modifies the decoded ordered data signal to identify display pattern component horizontal coordinates on the raster line to be scanned next, and transmits the modified data signal to a second output line. It is output to the second human power line of the intermediate buffer and stored there.

Also, the graphical pattern generator does not output a modified data signal to the second output line when no component of the display pattern is on a subsequent raster line to be scanned in the display field.

Embodiments of the present invention will be described in detail below with reference to the drawings.

The video generation circuit of the present invention, shown in FIG. 1, utilizes an "on-the-fly" refresh technique to dynamically generate a DTV display.

This video generation circuit includes a refresh buffer 28, an intermediate buffer 38, a vector generator 42 or a symbol generator 4.
0, and partial raster assembly storage (PRA)
(abbreviated as S) has been admonished since 44.

Refresh buffer 28 receives data signals representing pixels (graphical elements) in a format as shown in FIG. data words are read once per field for vectors and symbols configured as background and dynamic data.

Refresh buffer 28 is comprised of a control module and two storage modules capable of storing a total of eight half words.

Each half word consists of 16 data bits and 2 parity bits.

The primary function of refresh buffer 28 is to store encoded data to form a visual display.

Data received randomly from the digital computer via line 68 is stored in an ordered form by the Y line.

This allows reading of refresh buffer 28 on a line-by-line basis.

Details of this refresh buffer 28 are shown in FIG.

The formats of the data words shown in FIG. 2 include vector format, symbol format, index format, and empty slot format.

Vectors require slots of 4 half words per vector.

The symbols require slots of four half words per set of up to four front-lit symbols.

Single symbols also require slots of the same size, with the last 3
It has a space code for each symbol.

The meaning of each field in the format will be explained later.

Data words are transferred from the digital computer to refresh buffer 28 via shared bidirectional half-word bus 68.

Intermediate buffer 38 is a high speed, small capacity memory that receives data in encoded form from refresh buffer 28 and sends the data to symbol generator 40 or vector generator 42 as appropriate.

Intermediate buffer 38 receives from refresh buffer 28 two 32-bit words for each symbol or vector starting at the rask line.

In this data, the rask line is the display device 10 (see Figure 8).
is requested by intermediate buffer 38 when memory space becomes available.

Details of this intermediate buffer 38 are shown in FIG.

Each village of encoded data words is sent at high speed to the appropriate display generator (symbol generator 40 or vector generator 42) where it is converted to digital video data.

Since one vector or symbol may appear on multiple rask lines, symbol generator 40 or vector generator 42 modifies the encoded data word and then generates digital video data for the next rask line. This modified data word is rewritten via line 202 to intermediate buffer 38 for use in processing.

If conversion to video data is completed during the current rask line occurrence, that particular data word will not be rewritten to intermediate buffer 38. Intermediate buffer 38 consists of a preload area and an active area, and its total The capacity is 256 words.

However, the ■word consists of 32 bits.

Data words are transferred from the refresh buffer 28 to the preload area when storage space is no longer available, and then transferred from the preload area to the active area when required for display.

Symbol generator 40 utilizes programmable memory to convert encoded symbol data from intermediate buffer 38 into the appropriate symbol bit pattern for the rask line to be displayed.

The symbol memory 56 (FIG. 5) is connected to a host processing unit (host
Processor).

A capacity of up to 256 symbols can be provided.

Symbol memory 56 can store any dot matrix pattern within a 16x16 format.

Details of symbol generator 40 are shown in FIG.

Each word pair from intermediate buffer 38 provides up to four symbol codes.

Symbol generator 40 automatically sets the spacing between symbols and positions the symbols according to the space code field in the first word.

The spacing between symbols is specified by the higher-level processing unit.

Symbol generator 40 outputs data words to intermediate buffer 38.
The counter field in the word pair in intermediate buffer 38 is incremented before being rewritten to.

When the count value reaches O, the word is retrieved from intermediate buffer 38.

Vector generator 42 receives two data words from intermediate buffer 38 and uses these data words to determine which elements on each rask line constitute the vector.

All vectors are designated by the host processor as individual vectors starting at the top and working downwards on the display screen.

Details of vector generator 42 are shown in FIG.

The vector is expressed as an X and Y position, an inverse slope (ΔX2ΔY), and the number of Y lines in which the vector appears (Y length).

The origin of the XY coordinate is at the lower left end of the display section, and like normal XY coordinates, X increases in the positive direction as you proceed from left to right, and Y increases in the positive direction as you proceed from bottom to top.

Vector generator 42 uses the inverse slope to determine the number of elements on the current line and updates the X position for use on the next line.

Vector generator 42 also counts the number of Y lines backwards to determine the vector termination.

Using modified floating point techniques, each point in a vector can be contained within one display element of a theoretical line specified by a higher-level processing unit.

PRAS44 displays the entire two display rask lines in explicit format (
It is a high-speed memory that can store video (in unencoded video dot pattern format).

All vector and symbol dot pattern data is collected or assembled into a single line in PRAS 44 during line time prior to normal display operation.

If a video line is to be displayed, the PRAS line is read out at the video rate while the next line is read out at the second PRAS rate.
Details of AS line hair all hair all hair semple AS44 are in the 7th
As shown in the figure.

PRAS 44 greatly simplifies vector generator 42 and symbol generator 40, allowing digital video
Restrictions on data intersection are removed and there is no need to order display data by X position in intermediate buffer 38 or refresh buffer 28.

Vector generator 42 and symbol generator 40 are connected to three PRAs.
S44 can be driven.

These PRAS 44 are provided one for each primary color in order to drive the RGB (red, green, blue) color display monitor 10.

The digital video output signal from each PRAS 44 is sent to a video output driver 46 where it is combined with a synchronization signal sent over line 190 and converted into a composite video signal.

This composite video signal is transferred via line 192 to the DTV display.

One output drive 46 is required for each primary color.

The video generation circuit according to the invention is most suitable for use in a dynamic DTV system as shown in FIG. 8 for use in applications where high speed and accurate identification of information is of paramount importance. It can be well described.

A specific dynamic DTV system using the video generation circuit of the present invention will now be described by way of example.

However, the video generation circuit of the present invention is not limited to use in this dynamic DTV system, but can also be applied to other display systems.

The example dynamic DTV system consists of configuration hardware that provides color status indicators to each integrated display console, and each operator operating each integrated display console has a trackball and The program function may interact with the higher-level processing unit via the keyboard device.

Dynamic DTV uses multiple on-line graphical display controllers to convert computer data into randomly positioned vectors and symbols representing dynamic conditions.

In this case, annotated background graphics may be generated at the same time to make the application more suitable for dynamic DTV systems.

New TV nuclear technology is used to generate graphical displays.

When such techniques are used with hardware according to the present invention, flexible configurations, high availability, autonomous refresh (not done in the host processor), and independent operation of multiple integrated display consoles are possible. , simple assembly configuration (4 consoles per graphical display control), programmable control, off-line, on-line and in-line mobility and maintenance via disk and supporting software Desirable characteristics include flexibility, solid state design using monolithic integrated circuit technology, and IBM System/370 compatibility.

Various features of the graphical display of this dynamic DTV system include: 307,200 displayable elements in 460 (vertical) x 640 (horizontal) format, 8 colors (including black);
constant refresh rate of 30 frames per second, full display update in less than 1 second, up to 1700 vectors or up to 1700 random symbols per display, dynamic and background data selective updating, programmable character set of 255 symbols per display (16x16 element matrix), graphical displayability of entire vectors, data retention (data intersections are never erased), and the blinking or fading of individual vectors and symbols.

Referring to FIG. 8, the system consists of the following main functional devices.

The integrated display console 16 includes a color graphical display 10 and operator devices 12 and 14 for interacting with the system.

The console 16 includes an independently operating IBM keyboard supported by an alphanumeric keyboard 20 and a light ben 22.
A 3277 alphanumeric display 18 is also included.

The integrated display console 16 is connected online to equipment that can be used for backup or testing.

The graphical display controller 8 includes a programmable controller 4 for performing data formatting, operator equipment processing and control functions, and a disk for initial program loading and internally generated diagnostic routines. connection mechanism and four independent on-the-fly color graphics/symbol video generators 6.

Each video generator 6 has two
A video generation circuit according to the present invention shown in FIG. 1 is slightly modified by the addition of one PRAS 44 and two video mixers or video drivers 46.

The active graphics display controller 8 provides on-line capability for independent display channels.

The eleventh graphic display controller 8 can be used as a backup or spare.

Graphics patch panel 24 is designed to be reconfigurable and to increase availability of the graphics system.

This panel 24 is an operator device in which any one of the 44 color display channels from the 11 graphical display controllers 8 is associated with any one of up to 44 integrated display consoles 16. Allows to be manually connected via.

Alphanumeric patch panel 26 is designed to be reconfigurable and to increase availability of the IBM 3277 alphanumeric system.

This panel 26 has an 84
Any one of the alphanumeric display channels can be used to perform operations related to any of up to 84 I BM3277 alphanumeric display devices (39 console mount devices 18 and 45 free mount devices 27). Allows users to manually connect via their personal device.

Next, a more detailed description of the equipment of the system will be provided.

The dynamic DTV system of FIG. 8 connects two IBM System/370 Model 15
It is a versatile interactive color display system that can be connected to an 8MP computer.

This dynamic DTV system is a programmable controller with 4%
It uses a fast monolithic refresh buffer controlled by

Programmable controller 4 and 4 video generators 6
constitutes the graphic display control device 8.

Each video generator 6 within the graphics display controller 8 provides the necessary graphics signals and signals to drive a color TV monitor 10 capable of interaction with a program function keyboard 12 and a trackball 14 for graphics cursor control. Give control.

Display device 10, keyboard 12 and trackball 14
IBM 3277 display device 18, alphanumeric keyboard 20
and a light pen 22 are incorporated into the integrated display/operation console 16.

Although the alphanumeric units 18, 20 and 22 are physically part of the integrated display console 16, they are controlled separately by the IBM 3272 controller and can therefore be considered independent systems.

This dynamic DTV system consists of 10 graphical display controllers8
and 38 integrated display/operation consoles 16, and one graphic display control device 8k and one integrated display/operation console 16 (#39) as spares.

Each graphic display control device 8 can drive and control four integrated display consoles 16.

The use of graphical patch panels 24 allows each graphical display controller 8 to be connected to any of the four integrated display consoles 16, thus increasing flexibility and system reliability.

The 8-277 display mechanism may also be reconfigured with another independent alphanumeric patch panel 26.

The programmable controller 4 sends data words representing the vectors and symbols to be displayed to the video generation circuit of the present invention included in the graphical display controller 8.

This video generation circuit utilizes graphics/symbol-on-the-fly generation techniques to provide dynamic (rapidly updated) graphics and symbols and static background color displays.

This on-the-fly technique improves system performance and eliminates the need for the large raster assembly and refresh storage associated with DT systems.

The programmable control device 4 includes four display consoles 16
operates in conjunction with four independent color video generators 6 to service the individual requirements of the color video generators 6.

A disk attachment attached to the programmable controller 4 allows initial program loading and storage of diagnostic routines and test patterns for individually working each color display channel of the assembly.

Communication with the channels of the superordinate computer and processing of the operator-controlled dialogue device take place via an adapter attached to the programmable control device 4.

The main paths of data flow in the dynamic DTV system of FIG. 8 are between the host computer system and the graphic display control device 8 (via the IBM 2914 switching device 2);
and each graphic display control device 8 and its integrated display operation console 16
It is between a collection of.

Two stages of control are performed in this dynamic DTV system.

That is, (1) a graphic command issued from the host processing device and supplied to the graphic display control device 8 via the switching device (interface) 2; and (2) a programmable control device 4 within the graphic display control device 8. Control is provided by internal graphics side commands issued to each of the four associated video generators 6 and their refresh buffers 28.

As shown in detail in FIG. 9, graphical display controller 8 includes programmable controller 4, display adapter 30, manual input adapter 32, maintenance panel 34, and power system 36.
, and four video generation circuits 6 according to the invention (as described above, refresh buffer 28, intermediate buffer 38
, symbol generator 40, vector generator 42, PRAS44
, and a video output driver 46).

Various devices of the video generation circuit 28.3B, 40° 42.
44 and 46 are shown in channel units.

Details regarding the design will be discussed later.

The programmable control device 4 has an integrated monolithic memory 48 and 11 for external communication.
This is a program storage type processing device including a 0 bus 50.

The controller 4 communicates with a host computer (eg, a System/370 model 158MP) via a System/370 local channel adapter 52, a disk file 54 via a disk file adapter, and a display adapter 30. and interface with the video generator 6 and the integrated display console 16, respectively.

A control program loaded into integrated memory 48 from disk file 54 enables controller 4 to receive graphical commands and data via System/370 interface 52 from a host computer.

The controller 4 interprets the received graphics commands, processes the data as required, and forwards the graphics side commands and data to the appropriate video generator 6.

Further, the control device 4 waits for manual inputs from the integrated display console 16, and transfers them to the higher-level processing device based on an interrupt.

Controller 4 is capable of translating manual input from console 16 and controlling video generator 6 in an off-line manner with diagnostic routines stored in disk file 54.

This allows in-line operation such that one console 16 in a console assembly can be diagnosed off-line without affecting the operation of the other three consoles 16.

Display adapter 30 enables controller 4 to provide data and control signals to four independent video generators 6 on a multiplexed, on-demand basis.

The manual input adapter 32 is connected to the display adapter 30 and each operation console 1.
Graphical power at 6 provides multiple interfaces between a trackball 14 for crane positioning and a program function keyboard 12 for operator interaction.

Maintenance panel 34 contains control circuitry, switches and indicators for operating graphical display controller 8 off-line for diagnostic purposes.

Additionally, a single video generator 6 can be installed in such a way that it can be operated in a diagnostic mode independently from the host processor without affecting the operation of the other three video generators. A control mechanism 53 is also provided for operation in line mode.

Power system 36 receives line power to provide the desired voltage values necessary to operate graphical display controller 8 and all of its components.

As mentioned above, the integrated display console 16 is connected to the graphic display device 1.
0, a program function keyboard 12 and a trackball 14.

Graphics display 10 is a standard 19-inch 5-inch display with 30 frames per second refresh and 2-to-1
A 12-line RGS color TV monitor that receives data from a video generator 6 via three video coaxial cables.

The program function keyboard 12 is connected to the graphic display control device 8.
The operator's interaction power is supplied to the upper-level processing device via the

Trackball 14 is used by the operator to position a graphical cursor on the display screen.

When you move this trackball 14, in response,
The cursor moves on the color display under the control of the graphic display controller 8.

Trackball 14 and program function keyboard 12
is connected to the graphic display control device 8 via the manual input adapter 32.
interface with.

As shown in FIG. 8, the graphic patch panel 24 has three
It is used to interconnect eight integrated display consoles 16 and ten graphic display controllers 8, and on the input side each graphic display controller 8 (including a spare one) has four video generators. 176 connectors are provided for receiving four output cables (three video cables and one digital cable) from each video generator 6 in the video generator 6 (including the video generator 6).

The output side of this patch panel 24 is equipped with 176 connectors for 39 integrated display consoles 16 and for making it possible to expand the system by adding five more consoles 16. It will be done.

Internally, patch panel 24 provides short-term IJ-IJ-numeric interconnection between any integrated display console 16 and any graphical display controller 8 channels.

Although the IBM 3277 display 18 is not electrically part of the color graphics display system, it is provided with a separate alphanumeric patch panel 26 to allow for the necessary interconnections and reconfiguration.

Because the 3277 display 18 requires only one coaxial cable, the alphanumeric patch panel 26 has 84 3277 displays for the 39 3277 displays housed in the integrated display console 16 and another stand-alone 3277 display 27. has input connectors.

The graphical display controller 8 is a free-standing device that provides signals and controls used to support the four color graphical displays and associated operator equipment, requiring no operator intervention during its operation. does not require.

Programmable Controller 4: The controller 4 is a 16-bit general purpose programmable device that uses two's complement arithmetic.

Utilizing high speed and high density solid state logic, this device can be thought of as a device that can be plugged into the graphical display controller 8.

As shown in FIG. 9, the control unit 4 has a modular high speed monolithic memory 48 which can be implemented in units of 8 to 64 bytes.

The functions executed by the control device 4 in response to manual input from the integrated display console 16 include direct interface with the higher-level processing device, reception and translation of graphic commands from the higher-level processing device, and graphic data from the higher-level processing device. interface with and control of the refresh buffer 28 when updating, deleting, and changing the display, monitoring and transferring manual input from the integrated display console 16, status and information for transferring to the higher-level processing device. These include maintaining sensed information as well as controlling graphical cursors for each display.

The controller 4 is interrupt driven and has 16 bits of 110
The busbar 50 allows the installation to communicate with the device via a suitable adapter.

A special adapter installed in the control device 4
a file adapter, a system 7370 local channel adapter 52, and a display adapter 30.

Graphical display controller 8 has a small read/write disk file 54 that interfaces with 110 bus 50 via a disk file adapter.

Since monolithic memory 48 of controller 4 is volatile, the control program to be loaded into memory 48 during initial program loading is stored in disk file 54.

This disk file 54 also stores diagnostic programs and test patterns used to test the dynamic DTV system in an offline diagnostic mode.

Programmable controller 4 includes a System/370 local channel adapter 52 to enable communication between graphical display controller 8 and higher-level processing units.

This adapter 52 provides an 8-bit interface to the higher-level processing device and a 16-bit interface to the control device 4.
Provides a bit interface.

The graphical display controller 8 can be coupled to a higher-level processing unit via a block multichannel and can support burst mode data transfer rates of up to 700 bytes per second via an interface.

Display adapter 30 allows up to four independent video generator channels to be attached to programmable controller 4.

This adapter 30 interfaces with nine devices: four refresh buffers 28, four programmable symbol stores 56, and one manual adapter 32.

Additionally, adapter 30 receives control signals from a maintenance panel 34 and a synchronization generator.

The interface shown in FIG. 10 is based on the following lines.

(1) Address - 13-bit address bus connected to all nine devices.

The programmable control device 4 loads the adren,
A step amount of 0, 1, 2, or 4 can be specified after each read or write operation.

(2) Data Bus - 18-bit bidirectional bus used by all nine devices.

Of the 18 bits, 16 bits are for data and 2 bits are for perity bits.

(3) Manual Input Adapter Selection - Select manual input adapter 32 for read or write operations.

(4) Symbol Store Selection - Selects the symbol store 56 indicated by the channel identification bits for a read or write operation.

(5) Refresh Buffer Selection - Selects the refresh buffer 28 indicated by the channel identification bits for a read or write operation.

(6) Channel identification bit O and designates one of 1-4 symbol stores 56 or refresh buffers 28;

(7) Read request: Initiate a read operation at the specified address of the selected device.

The selected device places data on the data bus.

(8) Write Request--Starts a write operation at a specified address of a selected device.

The selected device uses the data on the data bus.

(9) Status Request - The device places status information on the data bus.

(10) Read/Write Complete - The requested data or status information has been placed on the data bus by the device, or the data to be written has been received by the device.

Display inhibit/unenable - If In, display is inhibited when the refresh buffer is selected.

If it is "0", display is not prohibited.

02) Channel (CH) N Parity Error - Indicates that a parity error occurred while reading the refresh buffer 28.

This is reset by a status request.

(13) Channel (CH) N On/Off Line - A signal from the maintenance panel 34 that indicates whether the channel is in an online or offline state for diagnostics.

Display adapter 30 interrupts programmable controller 4 whenever a channel goes on-line or off-line.

(14) Vertical Retrack - A signal from the sync generator and used by display adapter 30 to interrupt programmable controller 4 once per frame.

This is used to initiate polling of manual input adapter 32.

Next, a more detailed explanation of the video generation circuit according to the present invention will be provided.

Refresh buffer 28 receives data from programmable controller 4 via display adapter 30;
This data is read out to intermediate buffer 38 once per field for display, as commanded by the Y address.

The stored data consists of combinations of vectors and symbols configured as background and dynamic data.

Refresh buffer 28 is comprised of one control module and two storage modules providing a total of eight half words.

Each half word has 16 data bits and 2 parity bits.

The primary function of this refresh buffer 28 is to store encoded data to provide a visual display.

Data received randomly by the programmable controller 4 is stored in the form specified by the Y line.

This allows reading refresh buffer 28 on a line-by-line basis.

Data is stored in slots of refresh buffer 28 that are designated in a manner similar to indirect addressing (
4 half words per slot).

Each slot has a pointer field containing the address of another slot, so a group of slots can be concatenated into a list.

FIG. 11 shows such a list.

The first slot in this list is slot 4.

Slot 4 points to slot 7, slot 7 points to slot 2, and so on until we reach slot 5, the last slot in this list.

This is represented by a special control bit designated EOT (end of chain).

Such a list has extremely useful properties.

That is, a slot can be added to the head of the list without affecting any slots already in the list.

In FIG. 12, slot 12 has been added to the head of the list.

In this case, we only need to know that slot 4 was previously the head of the list.

Programmable controller 4 uses separate lists for background data and dynamic data on each Y line to organize the data in refresh buffer 28 into such linked lists.

These lists are accessed by indexes, which are tables of pointers.

Each rask line has an associated pair of index half words, one for background data and one for dynamic data.

These half words are stored in fixed storage locations in refresh buffer 28 at addresses directly related to the Y address of the data on the display screen.

When adding slot 12 to the list in Figure 11,
It is necessary to access the index and find that slot 4 was previously the head of this list, write slot number 4 to the pointer field of slot 12, and write slot number 12 to the index.

The index thus points to the new head of the list.

Just as slot 12 was added to the list and became the head of this list, the slot at the head of the list can also be removed.

In this case, the index is read and used to access slot 12.

The pointer for slot 12 includes slot number 4.

When this slot number 4 is loaded into the index,
Slot 12 is no longer on this list.

Slots 12 may be linked to another list.

The programmable controller 4 uses this function to manage empty slots.

Initially, empty slots are linked with a special pointer called the Next Empty Register (NER) pointer that points to the head of the list of empty slots.

Unlike the above-mentioned index, which is placed in the refresh buffer 28, this NER is placed in the programmable control unit 4.

However, it is also possible to place the NER in the refresh buffer 28.

When data requires one slot, this slot is taken from the empty list and concatenated to the appropriate Y-line list.

Once the data is cleared, the slot is relinked to an empty slot.

To read for display refresh, the index half word for the dynamic data of the desired Y line is accessed and the first slot of the list corresponding to this Y line is filled from there.

This data can be used while the pointer field of the first slot allows access of the next slot.

The last slot is recognized by its EOT bit,
A similar process is then repeated for background data.

Data for the next Y line is then read.

The memory containing eight half words is divided into two groups: index and data slots.

The index consists of 960 half-words, of which even-numbered words represent dynamic data and odd-numbered words represent background data.

The remainder of the memory is organized into data slots having four half words each.

These data slots start on double word boundaries.

Refresh buffer 28 communicates with programmable controller 4 via display adapter 30.

Data words are transferred from display adapter 30 to refresh buffer 28 via a shared bidirectional half-word bus.

All update and diagnostic operations are accomplished by a series of read and write fingers from the display adapter 30.

The programmable controller 4 can also be commanded to inhibit any display.

Once selected, refresh buffer 28 senses the inhibit/unenable line and inhibits or disables refresh depending on its state.

This feature allows 100% of the refresh buffer 28 time to be utilized for updating background data.

A complete display update is accomplished in less than 42 milliseconds in the worst case, and on average a display update (one frame) can be completed in less than 33 milliseconds.

Display operations are normally prohibited during the update.

The display adapter update format shown in FIG. 2 consists of a vector format, a symbol format, an index format, and an empty slot format.

The cursor is generated as a special symbol positioned by the programmable control device 4 and identified by the operator by its unique shape and color.

Instead of using such special symbols, two vectors can also be used.

The vector format requires four half-word slots per vector.

The symbol format requires slots of four half words for each set of up to four consecutive symbols.

Also, single symbols have spaces for the last three symbols.
Requires the same size slot with the code.

The refresh buffer data is stored in the second
It is received from display adapter 30 in the format shown and stored in refresh buffer 28.

The index format contains three fields:

(1) Pointer Field - The upper 11 bits of the address of the first data slot read to refresh the display.

(2) EOT field - If 1'', indicates no data.

(3) End of Display (EOD) Field - If 1'', indicates the last line of the display has been reached.

The vector format contains 11 fields.

(1) Pointer field - the upper 11 bits of the address of the next data slot to be read to refresh the display.

(2) Horizontal Line (HL) Field - If "1", indicates a horizontal line.

(3) Vector/Symbol (V/S) field -1'' indicates a vector.

(4) Flash (FL) Field - If 1'', the vector flashes at an IHz frequency (repeated on/off every 0.5 seconds).

(5) E OT field - If 1'', indicates that no more data slots specified by the Y address need be read from this list for display.

(6) Gradient field - If HL = “O”, the slope is a 16-bit inverse slope (△X/△Y), if H
If L="1'', it indicates the length of the line.

(7) X field - indicates the X starting position of the vector or the left edge of the horizontal line.

(8) Color field - consists of 3 bits and specifies one of seven colors.

(9) Shift Field - If 'O', the slope is decoded as a 6-bit integer and 10-bit decimal; if '1', it is decoded as a 10-bit integer and 6-bit decimal. .

00) Sign field - If O'', the vector goes from left to right; if ``1'', the vector goes from right to left.

All vectors go from top to bottom. (11) ΔY field - indicates the distance between the starting Y line and the ending Y line of the vector.

The symbol format contains 12 fields.

(1) Pointer field - same as vector format.

(2) Lower space field - see next section.

(3) Upper Space/Lower Space Fields - The Upper Space and Lower Space fields determine the spacing (0-31 rask elements) between the leading edges of the symbol defined by the slot.

(4) V/S field - "0" indicates a symbol. (
5) FL field - same as vector format.

(6) EOT field - same as vector format.

(7) X Feel Association - 1 Indicates the leftmost X position of the 16x16 array containing the first symbol.

(8) Color field □ Same as vector format.

(9) - (121 symbol field (St-84)) - Contains an 8-bit code used to specify the 14-character symbol.

The empty slot format contains two fields.

(1) Pointer field - the upper 11 bits of the address of the next slot in the list of empty slots.

(2) EOT field - If '1', indicates this slot is the last slot in the list of empty slots.

The interface between refresh buffer 28 and intermediate buffer 38 shown in FIG. 13 consists of five control lines and sixteen data lines 29.

Communication between them is initiated by data request lines.

Data is transferred on a request/response basis under the control of data supply lines and data receive lines.

The request continuation line is used during multiple transfer.

Another control line or word one supply line is the intermediate buffer 3
8 and refresh buffer 28 are controlled to operate based on address synchronization during multiplex transfer.

The data is transferred to intermediate buffer 38 in the same format as it was stored in refresh buffer 28, except that the 11 bit pointer field is replaced by a 9 bit Y line field.

Next, refresh buffer 28 is initialized, data is appended, data is deleted, and the background
Describes how read and write commands are used to erase data or dynamic data.

Initialization: Refresh buffer 28 must first be initialized before operation.

This is accomplished in two stages.

First, the index is preset by writing one half-word with EOT="1" into each index storage location of refresh buffer 28.

However, the last index storage location is EOD2''.
A half word with 0'' is written.

The data slots are then concatenated by writing to the first word of each slot except the last slot a half word with an EOT of O'' and containing the upper 11 bits of the address of the first half word of the next slot. be done.

The last slot is written with a half word containing EOT="1" and the programmable controller 4 loads the address of the first slot into its NER pointer.

In this way, the initial setting of refresh buffer 28 is completed.

Initialization is simplified by having all write commands specify display inhibition.

To maintain proper connectivity of refresh buffer 28, refresh buffer 28 is not only initialized when programmable controller 4 performs an initial program load, but also reinitialized when the entire display is erased. Set.

Adding data: To add a vector or a set of up to four symbols, the programmable controller 4 operates according to the following steps.

(1) Read the background index word or the dynamic index word as required for the Y line to which data is to be addressed.

(2) If the EOT bit in NER is 'O', read the first word of the slot pointed to by NER.

If EOT=“1”, all slots are full.

(3) Using the EOT bit and pointer from the index word and data from the higher processing unit, assemble the four half words and write the step 2 slot.

(4) Using the pointer from NER, write the pointer and EOT="O" to the index word of step 1.

(5) E from half word read in step 2
Write OT bit and pointer to NER.

This completes the data addition.

The slot at the beginning of the list of empty slots is selected and
is loaded, thus NER points to the next slot in this list.

The index points to the newly written slot,
On the other hand, this slot points to any previously written data.

Deletion of data: To delete a data item, the programmable control device 4 operates in the following steps.

(1) Read the background or dynamic index word for the Y line for which the data item is to be deleted.

(2) Use the pointer from the index to
Read slot.

If EOT2 is "1", the control device 4 notifies the higher-level processing device that it has not been found, and then exits from this routine.

(3) Compare the contents of the slot with the data to be deleted.

(4a) If there is a match, after writing the EOT bit and pointer from the slot to the index, step 7
Proceed to.

(4b) If there is a mismatch and the EOT of the slot is “l”
”, the routine exits after notifying the higher-level processing device that it was not found.

(4c) If there is a mismatch and the EOT of the slot is O”
If so, use the pointer from this slot to read the next slot.

(5) Compare the contents of the slot with the data to be deleted.

(6a) If there is no match and EOT=''1'', the routine exits after informing that it was not found.

(6b) If there is a mismatch and EOT-0”,
After reading the next slot using the pointer from the slot, return to step 5.

(6C) If there is a match, the EO from the matched slot
Write the T bit and pointer to the slot pointing to this matched slot.

(7) Write the EOT bit and pointer from NER to the matching slot.

(8) Load NER with EOT=0 and a pointer pointing to the matching slot.

This completes data deletion.

The data is placed in a list and bridged, or
If this data was the only item in the list, the index EOT is set to 1''.

Slots that contained data are prepended to the list of empty slots.

Erasing dynamic data: To erase all dynamic data, the programmable controller 4 operates in the following steps.

(1) Read the first dynamic index half word.

(2a) If EOT=“1”, proceed to step 7.

(2b) If EOT=“0”, read the first half word of the data slot using the index zointer.

(3a) If EOT="1", proceed to step 4.

(3b) If EOT=“0”, use the data slot pointer to read the first half word of the next data slot.

(4) NE in the first half word of the last data slot
Write R.

(5) Load EOT=''0'' and pointer from index to NER.

(6) Write EOT="1" to the index.

(7a) If this is the last dynamic index, exit this routine.

(7a) Otherwise, read the next dynamic index.

(8) Return to step 2.

This completes erasing.

The EOT bit of each dynamic index half-word is set to 1'' and all lists of dynamic data are concatenated to the list of empty slots.

If the command from the higher-level processing device is deletion-addition, new data can be added next.

Refresh buffer 28, shown in detail in FIG. 3, includes memory capable of storing eight half words and address and control logic, and interfaces with display adapter 30 and intermediate buffer 38.

Concurrent requests for services are handled by priority control 60
solved by.

When refresh buffer 28 is selected by display adapter 30 and priority control 60 permits, control logic 62, via memory address register multiplexer 64, selects display adapter 30's address bus 68'.
to the memory address register (MAR) 66 and initiate a read cycle or write cycle as required.

During a write cycle, data bus 68 of display adapter 30, which is the only source of data for refresh buffer 28, is loaded into memory 70.

During a read cycle, the data at the addressed storage location is loaded into memory data register (MDR) 72 and then gated through data gate 73 to data bus 6B of display adapter 30.

When the operation is complete, control logic 62 sets the read/write complete line, display adapter 30 de-energizes the request, and control logic 62 de-energizes the read/write complete signal.

At this time, display adapter 30 either turns off its refresh buffer select line or changes the address to request another memory operation.

When intermediate buffer 3B requests data and priority control 60 grants it, the read operation of refresh buffer 28 for display continues from where it was turned off.

For purposes of explanation, it is assumed that the first Y line is about to be read.

Control logic 62 gates the contents of refresh Y counter 63 via MAR multiplexer 64 and initiates a read cycle.

EOT when index word is in MDR72
/EOD detector 74 checks the EOT and EOD bits.

If EOT="1", there is no data, the refresh Y counter 63 is incremented, and the same operation is repeated.

When the last index word is read, this is 1
”, the status bit is set in the status unit 61 and the refresh Y counter 6
3 is reset for the next field.

When an index word with EOT 'O' is found,
The pointer field from MDR 72 is loaded into the upper 11 bits of MAR 66 and '0' is loaded into the lower 2 bits.

The first word of the selected data slot is then read.

The pointer field and EOT bit of this word are read into temporary address register (TAR) 76'\.

The selection gate 77 replaces this pointer with the number of the Y line,
Then, the data supply line to intermediate buffer 38 is set.

The intermediate buffer 3B sets a data receiving line after taking in the data.

The data supply line is deenergized.

However, refresh-buffer 28 does not wait, it advances MARB6, reads the second word and sends it to intermediate buffer 3B.

Intermediate buffer 38 can receive this word until it becomes available.

This continues until the fourth word, after which the first word's EOT (located in TAR 76) is examined.

If this is 1”, refresh Y counter 63
is incremented and the next index word is read.

On the other hand, if EOT is O”, TAR76 is MAR66
and the next data slot is read.

Two status bits are used in the status unit 61.

As previously discussed, the first status bit is set at the end of the display and reset at vertical retrack.

The second status bit represents the display inhibit/unenable status from the most recent selection by the programmable controller 4.

Priority control 60 examines these status bits and requests service.

The priority is determined such that the intermediate buffer 3B has the highest priority except when display is inhibited and during the period from display termination to vertical retracking.

However, if display adapter 30 has been granted service, display adapter 30 will continue to operate until the refresh buffer select line is deenergized.

Parity is checked by parity checker 67 on each storage read and parity errors are signaled to display adapter 30.

The programmable controller 4 can request the status of the refresh buffer 28 in which case the error bits (one for each half of the memory) and the inhibit/unenable bits are sent to the data via status gates 69. It is gated to busbar 68.

Another example of refresh buffer 28 may be a concatenated queue buffer as disclosed in US Pat. No. 3,906,480.

Next, the operation of the intermediate buffer 38 will be explained.

Intermediate buffer 38 serves as a high speed scratchpad memory for vector generator 42 and symbol generator 40, and as shown in FIG. input registers 78 and the necessary read/write addressing and control equipment for proper operation.

The memory is divided into two equal areas: an active area and a preload area.

Data is sequentially transferred by the Y line from the refresh buffer 28 to the 32-bit ASSET 1 register 81 to the dot-OR circuit 8 until the preload area is full.
3 and input register 78 to the preload area.

As each TV rask line is generated during PRAS 44, the data word for that rask line is read from the preload area via line 200 into the appropriate symbol generator 40 or vector generator 42.

Reading from the preload area continues until the data for the Y line being generated has been completely read or the preload area is empty.

Once a preloaded storage location has been read, it can be used for further data from refresh buffer 28.

The preload area contains 128 32-bit storage locations, and each vector/symbol group requires 64 bits or 2 storage locations, so at most 64 vector intersections/4 per line. symbol groups may be allowed.

The active area contains the data being displayed at any given line time.

The data is read for each line and stropped into the appropriate vector generator 42 or symbol generator 40, where it is modified and rewritten to the active area via line 202.

When vector generator 42 or symbol generator 40 detects the end for the data, it is not rewritten.

Active area reads and writes start from the same address.

The read read address is always compared to the last address written to the previous Y line.

If the comparison results in a match, this indicates that all data in the active region has been read and stropped into vector generator 42 or symbol generator 40.

At this time, the preload area is inspected for Y-line comparison,
Any available data is then read from this area.

Normal operation of the active area: The active area is from address OOO to 177 in octal notation.
Defined as the storage location up to.

Vector/symbol data is loaded in increments starting at address 000.

FIG. 14 shows the addressing logic 92 for the active area, and FIG. 15 shows the timing relationships of the various signals.

During horizontal blanking, the contents of the write counter 82 are stropped to the final address write register 84.

The counter 82 is then set to a starting value (ooo'+heli).

Vector/symbol read complete comparator 86 is examined and if the result is negative, by providing the contents of vector/symbol read counter 88 to address multiplexer 79 for addressing memory 80; Read recycling is initiated.

The function code is examined by the function decoder 87 and the data is loaded into the vector generator 42 or symbol generator 40.

Sample and read recycling is repeated until one of the following events occurs:

(1) A data supply signal is received from refresh buffer 28.

As a result, the read recycling in progress is terminated.

Control is then switched to the preload area and the data in refresh buffer 28 is transferred to line 29 . Assembly register 81. Appropriate preload addressing logic is applied via dot-OR circuit 83 and input register 78.

(2) The vector generator in use signal is the vector generator 42
When the word being received and read from is a vector word.

As a result, the intermediate buffer 3B is connected to the vector generator 42.
Waits until available or until condition 1 or 4 occurs.

(3) When a symbol generator busy signal is received from symbol generator 40 and the word being read is a symbol word.

This causes intermediate buffer 38 to wait until symbol generator 40 is available or until condition 1 or 4 occurs.

(4) A write request is received from symbol generator 40 or vector generator.

As a result, the symbolic data or vector data appears on the line 202.
and is loaded into input buffer register 78 via dot-OR circuit 83.

The read cycle in progress is terminated and a write cycle is initiated using the contents of vector/symbol write counter 82 as the address.

This counter 82 is then incremented.

Blinking operation: This is performed at the input to intermediate buffer 38.

The synchronization and timing generator produces a blinking signal that is ``1'' for 0.5 seconds and ``0'' for 0.5 seconds.

Whenever this blink signal is 1'', blink control logic 90 is activated and the data from refresh buffer 28 is
Sample words.

When a blink bit is detected, the write cycle is ignored and the symbol word or vector word associated with this blink bit is not loaded into intermediate buffer 38.

When the blink signal is 0'', blink control 90 is deactivated and all words are loaded into intermediate buffer 38.

Normal operation of the preload area: The preload area is defined as the storage locations from addresses 200 to 377 in octal notation.

FIG. 16 shows the necessary read/write address control logic 94 for the preload region.

The counters are the same as for the active region, except for the vector/symbol next Y line register 96 and the comparators 98, 86 and 102.

A write is initiated by refresh buffer 28, which loads the data word into the appropriate address in the preload area.

The Y address of the first word written to each sector is loaded from memory 80 via line 200 into the appropriate next Y line register 96.

When the active area is emptied, the contents of the Y line register are compared with the Y address (coming from the synchronization and timing generator) of the next line to be displayed.

If a comparison match is detected, a read cycle is initiated to strobe the data to the appropriate generator 40 or 42.

Read counter 88 is incremented and another read is initiated.

Then, the Y address of this word will be the next Y line and register 9.
6 and compared with the Y address of the next Y line.

This procedure continues until a Y code with no match is loaded.

At this time, the read counter 88 is not incremented and the read enable line remains deenergized until a compare match is again detected.

Address counters 82 and 8 for preload areas
B is a cyclic type.

At initialization, these counters are set to their minimum values.

Write counter 82 is incremented after each write from refresh buffer 28 until it reaches its maximum value.

When write counter 82 reaches its maximum value, the next write resets counter 82 to its minimum value.

Read counter 8B operates similarly and is incremented after each read operation.

Thus, write counter 82 is always ahead of or equal to read counter 88.

Write operations from refresh buffer 28 continue until the preload area is full.

At this time, the write counter 82 is considerably ahead of the read counter 88, so any further writing would result in writing over data that has not yet been read.

This condition is asserted when write address counter 82 is incremented at the end of each write cycle.

The contents of write address counter 82 are compared with the contents of read read address counter 88 in comparator 102, and when they are equal a signal is generated from detection device 103 indicating that the preload area is full.

No further write operations are initiated until at least one read operation is completed.

Read operations continue under the control of Y compare circuitry 82, 88 and 102 until the preload area is empty.

The preload area becomes empty when read counter 88 catches up with write counter 82.

This condition is checked at the end of each read cycle when the read counter is incremented.

Read read address counter 88 is compared to write address counter 82 and when they are equal a signal (EMPTY) is generated indicating that the preload area is empty.

No further read operations are initiated until at least one write operation is completed.

Data Initialization: Intermediate buffer 38 is initialized during each vertical blanking period by setting all counters 82 and 88 to their initial values.

The refresh buffer 28 is then written to fill the preload area of the memory 80 of the intermediate buffer 38 with all data starting at the top of the screen that is first loaded.

The Y-line comparison circuit 98 is activated and any data starting at the top of the screen is read from the preload area of the memory 80 and sent to the appropriate symbol generator 40 or vector generator 42 via line 200. be done.

A special control signal inhibits the generator 40 or 42 from modifying the data, and this data is transferred via line 202 to the active area of memory 80 in the intermediate buffer 38 in the same state as it was received. Will be written back.

This operation occurs when the active area of memory 80 becomes full (as detected by detector 89 in FIG. 14) or when the output of Y comparator circuit 98 goes low and no more data for that line address is available. It continues until it shows that it doesn't exist.

When the vertical blanking period ends, the read counter 8
8 is energized and 1 normal operation continues.

Symbol generator 40 can generate 256 programmable symbols, each defined by a 16x16 matrix.

Fonts of this size or smaller can be generated directly, while larger fonts can be generated by combining symbols.

Symbols are generated in groups of four.

The symbol generator 40 positions the symbol based on the top left X and Y address of the 16x16 matrix, accesses the symbol one segment at a time, and
Load to AS44.

The symbol word loaded into refresh buffer 28 includes an X address, an implied Y address, a color code (3 bits) and up to four symbol codes.

Additionally, another bit is added to specify the blinking attribute.

2. If 3 or 4 symbols are included in one data word, the color and blinking attributes apply to all.

FIG. 5 shows symbol generator 40 in detail, and FIG. 17 shows the timing relationships for sequential symbols.

When the data is read from intermediate buffer 38, it is in the following form.

32 bits 4 symbol codes 10 bits 5 bits in the X position of the leftmost bit of the leftmost symbol Spacing 1 bit Start field 4 bits Segment code 3 bits Color These are the symbol code registers 104. X starting address register 106. spacing register 108,
Starting finite register 100, segment counter 110 and segment code register 112, and color register 114 are each loaded, and the first symbol code is selected and input from register 104 to symbol memory 56.

Block MU located between register 104 and memory 56
X is a multiplexer.

(Same for other MUX blocks).

The starting field loaded into register 100 is
It is exclusive ORed with the display field signal from the synchronization and timing generator shown in FIG.

The spacing bits loaded into register 108 are used to generate Δ×.

This is sent to the X increment adder 109 after each symbol occurrence and then the X
Loaded into write register 116.

X increment adder 109 positions subsequent consecutive symbols at the appropriate X address by adding the correct X increment (spacing) to the starting X address loaded into register 106.

The symbol code register 104 can be loaded with up to four symbol codes, but if there are less than three symbol codes, the blank detector 105 will fill in the space.
Code detected.

As a result, symbol completion detector 111 detects no more PRAS
Skips to the next character without performing a cycle.

The segment code loaded into register 112 is
which line of the symbol is to be read from the symbol memory 56 in the symbol generator 40;
Used to address 6.

The segment code is also loaded into a counter 110, which is incremented each time a segment code is received.

That is, it is stepped for each rask line.

The incremented segment code is written back to intermediate buffer 38 via intermediate buffer input multiplexer gate N02 and line 202.

The information loaded into registers 100, 104, 106, 108 and 114 is similarly loaded into multiplexer gate 1.
02 and line 202 to intermediate buffer 38.

However, when symbol completion is indicated by the segment code and is detected by symbol completion detector 111, the symbol word containing this information is not rewritten to intermediate buffer 38.

Symbol memory 56 stores symbol codes from register 104;
Addressed by the segment code from register 112 and the start field from register 100, a particular segment of a particular symbol in memory 56 is provided to shift register 107 via an OR circuit.

A shift and load controller 113 that controls the shifting operations of this shift register 107 uses the lower two
A bit is received from the X write register 116 and based on the bit value, shift register 1'07 is shifted so that the symbol segment in shift register 107 is aligned with the word boundary of PRAS 44.

A feedback gate 103 connected to the shift register 107 is for writing a combination of several symbol segments into the PRAS 44 at the same time, the output of which is ORed with the symbol segment from the symbol memory 56 before Shift register 107 is loaded.

Symbol segment completion detector 115 detects that the symbol segment in shift register 107 has been transferred to PRAS 44 via line 182 and multiplexer MUX, and accordingly sends a symbol segment to symbol completion detector 111 and controller 117. Send control signals.

Symbol completion detector 111 detects symbol completion upon receiving this control signal and the detection signal from blank detector 105 or the final segment code from register 112.

Controller 117 receives control signals from symbol segment completion detector 115 and signals from shift/load controller 113 to control the operation of X-increment adder 109, described above.

Note that the hatched portion in "Output of symbol memory" in FIG. 17 indicates that the output of the symbol memory 56 is in an uncertain state.

This is because the access time of symbol memory 56 can vary between approximately 50 and 170 nanoseconds depending on the address, and the output of symbol memory 56 stabilizes at the end of the shaded portion.

Next, the vector generator 42 will be explained.

The vector data is transferred by the upper processing unit in a format as shown in FIG.

Each vector has its own starting point (designated as the uppermost point in the vector), length in the Y direction △Y
) and an inverse gradient (ΔX/ΔY, with positive and negative signs).

The vector generator 42 calculates that the length of the horizontal line segment is ΔX
/ΔY is used.

Adding or subtracting this value to the starting X address provides the starting point for the next line segment.

FIG. 18 simply shows this operation.

The starting X position, the ΔX/ΔY value and the ΔY value are received from intermediate buffer 38 via line 200 and loaded into the appropriate registers 118, 120 and 122, respectively.

Two transfers are required to collect all the necessary data.

The starting X position for the first horizontal line segment is transferred to the X register 124.

ΔX/ΔY is loaded into the ΔX register 126.

The value of ΔY is decreased by 2, and if zero detector 12
When it is detected that the value of △Y becomes O by B,
The X position values ±2ΔX/ΔY1ΔX/ΔY and ΔY are written back to intermediate buffer 38 via line 202 as the data needed to generate the next line segment of that field.

When ΔY becomes negative, the vector is completed and data is no longer written back.

Figure 19 shows coordinates X-70 from coordinates X=50 and Y=50.
and Y-42.

To obtain the closest approximation to the actual vector, the first and last horizontal line segments are 1/2△X/△Y as the addend.
Calculated using

Thus, the horizontal segment is x
In the line 49, the plot is plotted from X=52 to X-53. In the line 48, the plot is plotted from x=54 to X=56. be done.

The last segment is plotted from X=69 to X near 0.

FIG. 6 shows the flow of data in the vector generator 42.

X, △Y and △X/△Y are from intermediate buffer 38 to line 20
0 to registers 118, 122 and 120, respectively.

Other control information in vector format is in register 1.
23・\Loaded.

ΔX/ΔY is a 16 bit word with one shift control bit.

This shift control bit has 16 bits of △X/△Y of 2.
The upper 16 significant bits or the lower 16 of the 0-bit X value
determine which of the significant bits to be added to.

To align the ΔX/ΔY values to the correct locations in arithmetic logic units (ALUs) 134 and 136, this shift bit determines whether the current horizontal segment is the first or last horizontal segment to be generated. The multiple shift logic 130 is controlled in conjunction with a controller 132 that detects the .

If the shift bit is “l”, ΔX/ΔY is ALU
136, it is added to the upper significant bit of X (△
The most significant bit of X/ΔY is added to the most significant bit of X).

If the segment to be generated is the first or last segment, the value of ΔX/ΔY is shifted to the right by one bit (the most significant bit of ΔX/ΔY is the most significant bit of ΔX/ΔY).

In the ALU 136, it is added to the bit one digit lower than the most significant bit of X).

When a vector starts in the opposite field from the field being displayed, extra calculations are performed to generate the first segment.

The X register 124 is loaded with the value of X received from the intermediate buffer 38 plus 1/2 (ΔX/ΔY) + 1 (subtracted for vectors with positive slopes).

FIG. 19 shows an example; if line 49 is to be generated, address register 118 is initially loaded with 50.

1/2・△X/△Y=1.25, XIL/Jister 124 d50+1.25+1
→52 is loaded.

As shown, the value 52 is loaded into the X-registor 124,
The upper 10 significant bits of △X/△Y - 1 are △X
The data is loaded into the register 126.

For vectors with slopes greater than 45°, the ΔX register 126 is reset to O, thus writing a single element on each rask line.

For the first element of a positive vector whose slope is less than 45°, (1
/2) △X/△Y is subtracted.

In a 20-bit ALU 136, if the
If the sum or difference between the lower 10 significant bits of register 118 and △X/△Y causes a carry to or a borrow from the upper 10 significant bits, △X becomes △
It is exactly equal to X/△Y.

ΔY is decreased by 2 and its sign is checked.

If this is non-negative, the X address register 118
A new starting X address for must be determined.

Depending on the sign of the slope, 2△X/△Y becomes the X address/
It is added to or subtracted from the value in register 118.

The intermediate buffer 38 and the intermediate buffer input multiplexer 127 and the line 202 together with the
\It will be reloaded.

A negative ΔY means that the vector is complete, and when this condition is detected by detector 128, control logic 14
0 prohibits writing back of data in the intermediate buffer 38.\.

The upper eight significant bits of the XI register 124 are PRAS.
44 (see FIG. 7) and the X-length controller 142.

The value of the ΔX register 126 is sent to the X shift controller 146 and the O detector 148.

The PRAS 44 has a primary PRAS and a secondary PRAS that receive 4 bits of vector data.

For primary PRAS-\ transfers, each bit transferred represents 32 bits of data.

Thus, in a 4-bit transfer of the main PRAS-\, 128 bits of data are actually transferred.

For the secondary PRAS, each bit transferred represents only one bit.

The selection of the primary PRAS and secondary PRAS is performed by control logic 140.

For transfers to the secondary PRAS, the two least significant bits of Xl are decoded via the X-length controller 142 to provide a four-bit word with a one in the bit position corresponding to the starting X address.

The value of ΔX1 determines the number of ones to be written.

On the first write to the secondary PRAS, Δ
Xl is compared with the two least significant bits of Xl.

This number is ΔX to find out the number of bits written.
Subtracted from 1.

A 4-bit word (all ones) is then written to PRAS 44, and the upper eight bits of ΔX1 are incremented backwards until a zero is detected.

The two least significant bits of ΔX are then decoded to generate the number of 1''s that are still to be written.

Then another 4 bits with only these bits set to 1.
The bit is written to PRAS 44, thus completing vector generation.

For vectors with small angles, it is desirable to reduce the number of 4-bit transfers to the secondary PRAS by transferring them to the primary PRAS.

During vector generation, when the 32-bit X address boundary is reached, the upper five bits of ΔX are examined.

If not, the two least significant bits of these five bits are sent to the X shift controller 146 and the corresponding bits of X are sent to the X length controller 142.

The operation is performed in parallel with the secondary PRAS transfer operation.

When an O is detected in the upper five bits of X, control logic 140 switches the transfer mode to a secondary PRAS\transfer to complete the vector.

When the HL bit loaded into the register 123 is "l" and the vector to be generated is a dash line (horizontal line), the dash control device responds to the HL bit and the value O of ΔY loaded into the register 122. 138 operates.

The operation of the vector generator in this case is roughly the same as the horizontal segment generation described above, but since the horizontal vector occurs only on one Y line, it generates the displayed element on the next Y line. It is not necessary to write the modified data back to the intermediate buffer in order to do so.

As shown in FIG. 7, PRAS44 is basically:
Two single line buffers (memories) operating in an A-B configuration
150 and 152.

While one buffer is being read and displayed, the other buffer is being loaded with data for the next line.

The data is in the form of 4-bit words and is sent to vector generator 42.
from symbol generator 40 via line 185 and from symbol generator 40 via line 182
is loaded to PRAS44 via.

Memories 150 and 152 of PRAS 44 are controlled so that only ones are written.

This allows data to be accumulated. Thus, there are no restrictions on the intersection of vectors or symbols, since any number of data intersections can occur at a given point.

As explained earlier, there are actually two PRAS, namely:
There is a 20-bit long main PRAS in which each bit represents a series of 32 bits on the raster line, and a secondary PRAS that represents a point-to-point image of the raster line.

The main PRAS is used only for vector generation.

Next, the refresh cycle operation of PRAS 44 will be explained.

This refresh cycle consists of a read cycle followed by a write cycle.

To return line buffers 150 and 152 to an all O state so that data for the next line can be loaded.
An erase operation is performed.

Buffer select flip-flop 154 selects which of line buffers 150 and 152 should be refreshed.

Address multiplexers 160 and 162 are then activated to gate the contents of read address counter 164 to the correct line buffer 150 or 152.

The data line is set to write a zero and the input data multiplexers 156 and 158 are set to provide a write enable pulse.

Output multiplexer 166 is also set to read from the correct buffer 150 or 152.

FIG. 20 shows the timing of the refresh cycle.

Data is read into parallel-to-serial (P/S) converter 168 under control of read controller 172, and then a write enable pulse is generated.

The data line is held at 0, which resets all bits.

The output of P/S converter 168 is a serial digital video stream containing vector and symbolic video.

The outputs of the primary PRAS and secondary PRAS are OR'd together, thus producing a serial stream of 32 1's of 1's from the primary PRAS.

Note that the shaded area in FIG. 20 indicates an uncertain state due to differences in register propagation delays and changes in memory access time (which differs depending on the address).

Refresh? Line buffers 150 or 152 that are not in the U state operate under iodine cycles.

In this operating state, data to be displayed on the primary raster line is written.

Input data multiplexers 156 and 158 and address multiplexers 160 and 162 are set to select data from either vector generator 42 or symbol generator 40.

The data to be written is input data multiplexer 1
71 to input register 170 and the address to be written to is stropped to write address counter 144 via input address multiplexer 143.

Since only a "1" is being written, the data input to the line buffer is set to a "1".

Data multiplexers 156 and 158 select the output of the data register that is used to set the write enable input of the line buffer.

In this manner, only the storage location corresponding to a 1'' in the data register receives the write enable signal under the control of write controller 174.

A 0 in a data word does not erase a previously written 1''.

The loading operation to input register 170 continues and write counter 144 is incremented until the operation is complete.

Since symbol and vector data are always loaded from left to right, write address counter 144 only needs to increment and does not need to increment backwards.

The timing relationships for such a write cycle are shown in the lower portion of FIG.

The video output from the control device 8 to the console 16 is as follows.

Supplied via three cables.

These cables provide the red, edge and blue primary color signals to the TV monitor 10.

One of these also includes synchronization information so that the color monitors can be properly synchronized.

The video waveform may conform to ELA standard R8-170 specifications.

This gives a 30Hz refresh, 2:1 interlaced raster.

3.58ME (z color burst is not used.

The reason is that the chrominance signal is sent to the monitor via three separate lines representing the red, blue and edge video signals, and is not combined as is the case with encoded chrominance signals. This is because it is not sent over a single line in any form.

The use of separate chroma signals provides a wider bandwidth of colors (up to 7ME (z)) than with coded chroma signals.

Figure 21a shows the details of the sync generator and Figure 21b shows the resulting raster.

In Figure 21b the entire raster is shown, including invisible blank areas.

The horizontal number represents the number of bits per raster line, and the vertical number represents the number of raster lines.

To generate the basic clock signal for the raster line,
A fundamental oscillator 172 of 11.97 MHz is used.

This bit rate is divided by 380 counter 174 and from this a blanking signal is output by decoder 176.
The synchronization signal, equalization signal and vertical synchronization signal are decoded.

All of these are twice the linear rate (31500).

The outputs of the divide-by-525 counter 178 and the divide-by-2 counter 180 are decoded by a decoder 302, and the outputs of the divide-by-525 counter 178 and the divide-by-2 counter 180 are decoded by a decoder 302, and the outputs of the even-number display field are , and for odd display fields, the odd signal.

The decoder 302 is also operated to select the equalization pulse and the vertical sync pulse at appropriate times to generate a composite waveform.

As is clear from the foregoing description, the video generation circuit according to the present invention improves the conventional video generation circuit by cyclically storing display data in encoded form, which is sequentially modified as raster fields are generated. Graphical display data and alphanumeric display data can be stored so that they can be accessed for display even more efficiently.

Although PRAS 44 has been described as storing two raster lines of video output data, it is possible to modify the system to use a PRAS that stores more raster lines.

It is also possible to change the number of raster lines over which data can be sorted in the refresh buffer.

Although the video generation circuit according to the invention has been described as being used in a dynamic DTV system, this does not imply any application of the invention to other display systems that use "on-the-fly" refresh techniques. It's not a hindrance.

[Brief explanation of drawings]

1 is a simplified block diagram of a video generation circuit according to the invention; FIG. 2 is a diagram illustrating the format of a data word input to refresh buffer 2B; and FIG. 3 is a detailed block diagram of refresh buffer 28. , FIG. 4 is a detailed block diagram of intermediate buffer 38, FIG. 5 is a detailed block diagram of symbol generator 40, FIG. 6 is a detailed block diagram of vector generator 42, and FIG. 7 is a detailed block diagram of PRAS 44. 8 is a block diagram of the dynamic DTV system, FIG. 9 is a detailed block diagram of the graphic display control device 8,
Figure 10 shows the wiring of the display adapter interface; Figure 11 shows the linked list in the refresh buffer for the first load operation;
Figure 2 shows the linked list in the refresh buffer for the second load operation, Figure 13 shows the interface between the refresh buffer and the intermediate buffer, and Figure 14 shows the address for the intermediate buffer. A block diagram of the addressing logic; FIG. 15 shows the timing for intermediate buffers; FIG. 16 shows a detailed block diagram of the preload addressing logic 94; FIG. 17 shows the timing for sequential symbols. 18 is a simple block diagram of the vector generator 42, FIG. 19 is a diagram showing an example of the operation of the vector generator 42, and FIG. 20 is a PRA
FIG. 21a is a block diagram of the sync generator, and FIG. 21b is a diagram illustrating the resulting raster. 2...Switching device, 4...Programmable control device, 6...Video generator, 8...
...Graphic display control device, 10...Color graphic display device, 12...Program function keyboard,
14...Trackball. 16... Integrated display operation console, 1B... Alphanumeric display device, 20... Alphanumeric keyboard, 2
2... Light pen, 24... Graphic patch panel, 26... Alphanumeric patch panel, 27... Alphanumeric display device. 28...°Ritzsch Buffer, 30...
・・Display adapter Kyu 32・・・・Manual input adapter,
34... Maintenance panel, 36... Power system, 38... Intermediate buffer, 40...
...Symbol generator, 42...Vector generator, 4
4...Partial raster assembly storage (PR
AS), 46... Video output drive device, 4B.
...Monolithic memory, 50...1
10 Busbar, 52...Local chillanel adapter, 54...Disk file.

Claims (1)

[Scope of Claims] 1. A video generation circuit for converting a data signal representing a graphic pattern irregularly received from a host processing device into a sequential video signal, which receives the data signal and converts it into a sequential video signal for each raster line. a refresh buffer for storing ordered data signals with the raster line as the starting raster line, and storing the ordered data signals for each display field before displaying the pattern, and scanning the data signals for line scanning. an intermediate buffer having a first input power connected to the output of the refresh buffer for outputting in synchronization with the refresh buffer; and an intermediate buffer connected to the output of the intermediate buffer for decoding the ordered data signal from the intermediate buffer. The components of the above pattern that are on the raster line to be scanned are
a graphical pattern generator generating to an output line; and a partial raster assembly storage device connected to the first output line of the graphical pattern generator for storing components of the pattern that lie on the raster line to be scanned. and the graphical pattern generator modifies the decoded data signal to identify the horizontal coordinates of the components of the pattern on the raster line to be scanned, and transmits the modified data signal to the a second input line of said intermediate buffer via a second output line for rewriting said intermediate buffer; A video generation circuit characterized in that it does not supply a modified data signal to two output lines.