JPS5845814B2 - Semiconductor device with laminated metal electrodes - Google Patents
Semiconductor device with laminated metal electrodesInfo
- Publication number
- JPS5845814B2 JPS5845814B2 JP51046826A JP4682676A JPS5845814B2 JP S5845814 B2 JPS5845814 B2 JP S5845814B2 JP 51046826 A JP51046826 A JP 51046826A JP 4682676 A JP4682676 A JP 4682676A JP S5845814 B2 JPS5845814 B2 JP S5845814B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- nickel
- gold
- electrode
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/30—Die-attach connectors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/073—Connecting or disconnecting of die-attach connectors
Landscapes
- Die Bonding (AREA)
Abstract
Description
【発明の詳細な説明】 本発明は、半導体装置特にその電極構造に係わる。[Detailed description of the invention] The present invention relates to a semiconductor device, particularly its electrode structure.
半導体装置例えば単体のトランジスタにおいては、通常
第1図に示すようにコレクタとなるシリコン半導体基体
1の一面上にベース領域2及びエミッタ領域3が形成さ
れ、べ″−ス電極B及びエミッタ電極Eが上面に形成さ
れると共に裏面にコレクタ電極Cが形成され、このコレ
クタ電極Cが所定のヘッダー4の導電層5に直接半田6
を介して取付けられるようになされている。In a semiconductor device, for example, a single transistor, normally, as shown in FIG. 1, a base region 2 and an emitter region 3 are formed on one surface of a silicon semiconductor substrate 1 serving as a collector, and a base electrode B and an emitter electrode E are formed. A collector electrode C is formed on the top surface and the back surface, and this collector electrode C is directly soldered 6 to the conductive layer 5 of a predetermined header 4.
It is designed to be installed through.
従来、ヘッダーに直接半田付けされる電極、即ちこの場
合コレクタ電極Cの電極構造としては、シリコン基体1
の裏面に直接ニッケルNi層を無電解メッキにて被着し
て構成するか、金Au層を直接蒸着するか、或は金Au
とニッケルNiの積層金属又は金AuとニッケルNiと
銀Agの積層金属等によって構成していた。Conventionally, the electrode structure of the electrode directly soldered to the header, that is, the collector electrode C in this case, is a silicon substrate 1.
Either a nickel-Ni layer is deposited directly on the back surface of the nickel layer by electroless plating, a gold-Au layer is directly deposited on the back surface of the nickel layer, or a gold-Au layer is directly deposited on the back surface of the
It was composed of a laminated metal of nickel and Ni, or a laminated metal of gold Au, nickel Ni, and silver Ag.
しかし乍ら、これら従来の電極構造は夫々次のような欠
点があった。However, each of these conventional electrode structures has the following drawbacks.
例えばシリコン基体1に直接ニッケルNi層を無電解メ
ッキしてコレクタ電極Cを形成した場合には、基体の不
純物濃度がl 018 atoms/−以上でないとオ
ーミック接続がとりにくく、特に基体1がP形の場合に
はN i3Pが析出しオーミック接続ができない。For example, if the collector electrode C is formed by electroless plating a nickel Ni layer directly on the silicon substrate 1, it will be difficult to establish an ohmic connection unless the impurity concentration of the substrate is 1018 atoms/- or higher, especially if the substrate 1 is P-type. In this case, Ni3P precipitates and ohmic connection cannot be established.
又、金Auを蒸着した場合には金シリコン共晶の硬度が
比較的大きいのでペレットが大きいと割れ易くなり、M
OS−IC等に於ては不適当であった。In addition, when gold-Au is vapor-deposited, the hardness of the gold-silicon eutectic is relatively high, so if the pellet is large, it will easily break.
It was inappropriate for OS-IC and the like.
又金Au及びニッケルNiの積層金属を用いた場合には
、アロイ処理して後冷却したときにニッケルNi層にひ
び割れが生じそこに半田が浸み込んで電極剥離が生じ易
く、また金とニッケルとの相互拡散によってニッケル面
の亀裂、或はシリコン−金−ニッケル合金が生じて半田
付けの作業性を悪くしていた。In addition, when a laminated metal of gold-Au and nickel-Ni is used, when the nickel-Ni layer is cooled after alloying, the nickel-Ni layer cracks and the solder seeps into the cracks, causing electrode peeling. Cracks in the nickel surface or a silicon-gold-nickel alloy are formed due to interdiffusion with the nickel metal, which impairs soldering workability.
さらに、金ニッケルー銀の積層金属による電極は半導体
集積回路ICなどに用いられているが、例えば単体のパ
ワートランジスタなどに応用したときには、半田量が多
いこともあって発熱したときに半田によって銀が浸蝕さ
れ、さらに金及びニッケルの相互拡散作用で金も半田に
浸蝕され、結果的に電極のヘッダーに対する接着強度が
劣下する欠点があった。Furthermore, electrodes made of gold-nickel-silver laminated metals are used in semiconductor integrated circuit ICs, etc., but when applied to single-piece power transistors, for example, the amount of solder is large, and when heat is generated, the silver is removed by the solder. Furthermore, due to mutual diffusion of gold and nickel, the gold is also corroded by the solder, resulting in a disadvantage in that the adhesive strength of the electrode to the header deteriorates.
本発明は、このような点に鑑みヘッダーに対する接着強
度並びにオーミック接続の良好な電極を有する半導体装
置を提供するものである。In view of these points, the present invention provides a semiconductor device having electrodes with good adhesion strength and ohmic connection to a header.
以下、第2図を用いて本発明による半導体装置の一例を
シリコントランジスタに適用した場合につき説明する。An example of a semiconductor device according to the present invention applied to a silicon transistor will be described below with reference to FIG.
第2図において、1はコレクタとなるシリコン単結晶基
体を示し、その−面上にベース領域2及びエミッタ領域
3が順次拡散によって形成され、ソノヘース領域2及び
エミッタ領域3上に夫々ベース電極B及びエミック電極
Eが形成されると共(こ基体1の裏面にコレクタ電極C
が形成され、このコレクタ電極Cが所定のヘッダー4の
導電層5上に直接半田箔6を介して取付けられる。In FIG. 2, reference numeral 1 denotes a silicon single crystal substrate serving as a collector, and a base region 2 and an emitter region 3 are sequentially formed on the negative surface thereof by diffusion, and a base electrode B and a While the emic electrode E is formed (the collector electrode C is formed on the back surface of the base 1),
is formed, and this collector electrode C is attached directly onto the conductive layer 5 of a predetermined header 4 via a solder foil 6.
ヘッダー4の導電層5はニッケルメッキ又は銀メッキ等
にて形成される。The conductive layer 5 of the header 4 is formed by nickel plating, silver plating, or the like.
又半田箔6としては、鉛Pb:90重量%、錫Sn :
9重量%及び銀Ag:1重量%よりなる合金箔が用い
られる。Further, as the solder foil 6, lead Pb: 90% by weight, tin Sn:
An alloy foil consisting of 9% by weight and 1% by weight of silver and Ag is used.
なお7はS iO2等よりなる絶縁保護膜である。Note that 7 is an insulating protective film made of SiO2 or the like.
本発明は、斯るトランジスタに於てそのヘッダー4の導
電層5に半田箔6を介して直接取付けられる電極、即ち
コレクタ電極Cを基体1の裏面に順次に被着した金Au
を主体とする第1の層8、チタンT1よりなる第2の層
9及びニッケルNiよりなる第3の層10より成る積層
金属11にて構成する。In the present invention, in such a transistor, an electrode that is directly attached to the conductive layer 5 of the header 4 via a solder foil 6, that is, a collector electrode C, is made of a gold Au layer sequentially deposited on the back surface of the substrate 1.
It is composed of a laminated metal 11 consisting of a first layer 8 mainly made of titanium T1, a second layer 9 made of titanium T1, and a third layer 10 made of nickel Ni.
金を主体とする第1の層8としては、基体1がN形のと
きには砒素Asを0.3%程度含む金Au層にて形成し
、基体1がP形のときには金Auのみの層(こて形成す
る。The first layer 8 mainly made of gold is formed of a gold-Au layer containing approximately 0.3% arsenic As when the base 1 is N-type, and is formed of a gold-Au layer containing about 0.3% of arsenic As when the base 1 is P-type. Trowel form.
各金属層8,9及び10の厚みとしては、夫々層8が5
00人〜1500人の範囲、層9が500A〜2000
人の範囲、層10が0.3μ〜1.5μの範囲が好まし
い。The thickness of each metal layer 8, 9, and 10 is as follows:
Range of 00 to 1500 people, layer 9 is 500A to 2000
In the human range, the layer 10 preferably ranges from 0.3μ to 1.5μ.
その理由は、例えば金を主体とする層8の厚みが500
人より少ないと基体1に対するオーミック接続に支障を
来たし、1500Aを越えて2000〜3000人程度
になるとニッケル面に亀裂を生せしめる。The reason for this is that, for example, the thickness of the layer 8 mainly made of gold is 500 mm.
If the number is less than the number of people, the ohmic connection to the base 1 will be hindered, and if it exceeds 1500A and the number of people is about 2000 to 3000, cracks will occur on the nickel surface.
又、チタン層9は金を主体とする層8とニッケル層10
の相互拡散を防止するもので、その厚みが500人より
少ないと相互拡散の防止効果が著しく減少し、2000
人を越えるとチタン層9自体に亀裂を生じて好ましくな
い。Further, the titanium layer 9 includes a layer 8 mainly composed of gold and a nickel layer 10.
If the thickness of the layer is less than 500 people, the effect of preventing mutual diffusion will be significantly reduced;
If it exceeds the number of people, cracks will occur in the titanium layer 9 itself, which is not preferable.
さらに、ニッケル層10に関しては、その厚みが0.3
μ以上であれば半田付けの際に半田箔6中の錫Snと反
応しても必要量残るに十分であり、反面1.5μを越え
るとニッケル層自体のストレスでチタン層9から剥れ易
くなり、またニッケル層10の抵抗が無視できなくなっ
て特性上不利な傾向となる。Furthermore, regarding the nickel layer 10, its thickness is 0.3
If it is more than 1.5μ, it is sufficient to remain in the necessary amount even if it reacts with the tin Sn in the solder foil 6 during soldering.On the other hand, if it exceeds 1.5μ, the nickel layer tends to peel off from the titanium layer 9 due to the stress of itself. Also, the resistance of the nickel layer 10 cannot be ignored, which tends to be disadvantageous in terms of characteristics.
積層金属11の形成は次のようにして行う。Formation of the laminated metal 11 is performed as follows.
先づコレクタ電極を形成すべき基体1の裏面を除く他部
表面をワックス又はレジストで保護し、基体裏面に対し
濃フッ化アンモニウム(NH4F )溶液にて5分、フ
ッ酸溶液(H2O:HF=5 : 1 )にて25分の
処理を行って表面酸化膜を除去し、蒸着の前処理を行う
。First, protect the other surfaces of the substrate 1 except for the back surface on which the collector electrode is to be formed with wax or resist, and soak the back surface of the substrate in a concentrated ammonium fluoride (NH4F) solution for 5 minutes and then apply a hydrofluoric acid solution (H2O:HF= 5:1) for 25 minutes to remove the surface oxide film and perform pretreatment for vapor deposition.
次に基体1を蒸着装置内に配置し、最初にAsを含むA
u(N形基体の場合)を抵抗蒸発源より蒸発せしめ基体
裏面にAuを主体とする層8を被着する。Next, the substrate 1 is placed in a vapor deposition apparatus, and A containing As is first
(in the case of an N-type substrate) is evaporated from a resistive evaporation source, and a layer 8 mainly composed of Au is deposited on the back surface of the substrate.
次にTi及びNiを順次エレクトロンビーム蒸発源にて
蒸発せしめ層8上にチタン層9及びニッケル層10を順
次蒸着する。Next, Ti and Ni are sequentially evaporated using an electron beam evaporation source, and a titanium layer 9 and a nickel layer 10 are sequentially deposited on the layer 8.
なおP形基体の場合にはAu、Ti及びNiを一連のエ
レクトロンビーム蒸着にて行い得る。In the case of a P type substrate, Au, Ti and Ni can be deposited by a series of electron beam evaporations.
次に連続的に蒸着された層8,9及び10を有する基体
1を380°C〜400℃ピーク温度でフラッシュアロ
イして電極Cを形成する。The substrate 1 with successively deposited layers 8, 9 and 10 is then flash alloyed to form the electrode C at a peak temperature of 380 DEG C. to 400 DEG C.
上述せる電極構造によれば、金を主体とする層8が直接
シリコン基体1に接触されている為にオーミック性が良
くなる。According to the electrode structure described above, since the layer 8 mainly composed of gold is in direct contact with the silicon substrate 1, ohmic properties are improved.
しかも金を主体とする層8とニッケル層10の間にチタ
ン層9が介挿されている為に金とニッケル間の相互拡散
が防止されシリコン−金−ニッケルの合金化による被着
強度の劣化、或は半田による侵蝕剥離が回避され確実な
半田付けが出来る。Moreover, since the titanium layer 9 is interposed between the layer 8 mainly composed of gold and the nickel layer 10, mutual diffusion between gold and nickel is prevented, and the adhesion strength deteriorates due to alloying of silicon-gold-nickel. Alternatively, corrosion and peeling due to solder can be avoided and reliable soldering can be achieved.
又、オーミック性が良いのでトランジスタに於ては飽和
時のコレクターエミッタ間電圧■。Also, because of its good ohmic properties, the collector-emitter voltage at saturation in transistors is ■.
B(set)が改善され、また半田付けの際下層金属が
ニッケル層10のために半田の侵蝕が出土されて劣化現
象がなく熱の伝導特性即ち熱抵抗θTの改善が図れる。B(set) is improved, and since the underlying metal is the nickel layer 10 during soldering, corrosion of the solder is eliminated and there is no deterioration phenomenon, and the heat conduction property, that is, the thermal resistance θT can be improved.
尚、上側ではトランジスタのコレクタ電極に適用したが
、パワートランジスタ等の表面電極(ベース及びエミツ
ク電極)或は他の一般の半導体素子の電極にも利用でき
る。Although the upper electrode is applied to the collector electrode of a transistor, it can also be used for surface electrodes (base and emitter electrodes) of power transistors, etc., or electrodes of other general semiconductor devices.
第1図は従来の半導体装置の一例を示す断面図、第2図
は本発明による半導体装置の一例を示す断面図である。
1はコレクタとなる半導体基体、2はベース領域、3は
エミッタ領域、4はヘッダー、5は導電層、6は半田箔
、8は金を主体とする層、9はチタン層、10はニッケ
ル層、Cはコレクタ電極、Bはベース電極、Eはエミツ
ク電極である。FIG. 1 is a sectional view showing an example of a conventional semiconductor device, and FIG. 2 is a sectional view showing an example of a semiconductor device according to the present invention. 1 is a semiconductor substrate serving as a collector, 2 is a base region, 3 is an emitter region, 4 is a header, 5 is a conductive layer, 6 is a solder foil, 8 is a layer mainly made of gold, 9 is a titanium layer, and 10 is a nickel layer. , C is a collector electrode, B is a base electrode, and E is an emitter electrode.
Claims (1)
る層、チタン層及びニッケル層を被着してなる積層金属
電極が形成され、上記金を主体とする層の厚みが500
人〜1500人の範囲に、上記チタン層の厚みが500
λ〜2000Aの範囲に、上記ニッケル層の厚みが0.
3μ〜1.5μの範囲に夫々選定されて戒る積層金属電
極を有する半導体装置。1 A laminated metal electrode is formed by sequentially depositing a gold-based layer, a titanium layer, and a nickel layer on the semiconductor region where the electrode is to be formed, and the thickness of the gold-based layer is 500 mm.
The thickness of the titanium layer is 500 to 1,500 people.
In the range of λ to 2000A, the thickness of the nickel layer is 0.
A semiconductor device having laminated metal electrodes each having a thickness in the range of 3μ to 1.5μ.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP51046826A JPS5845814B2 (en) | 1976-04-23 | 1976-04-23 | Semiconductor device with laminated metal electrodes |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP51046826A JPS5845814B2 (en) | 1976-04-23 | 1976-04-23 | Semiconductor device with laminated metal electrodes |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS52129376A JPS52129376A (en) | 1977-10-29 |
| JPS5845814B2 true JPS5845814B2 (en) | 1983-10-12 |
Family
ID=12758121
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP51046826A Expired JPS5845814B2 (en) | 1976-04-23 | 1976-04-23 | Semiconductor device with laminated metal electrodes |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5845814B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60110127A (en) * | 1983-11-18 | 1985-06-15 | Sony Corp | Semiconductor device having laminated metal electrode |
-
1976
- 1976-04-23 JP JP51046826A patent/JPS5845814B2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS52129376A (en) | 1977-10-29 |
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