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JPS5845832B2 - Kinzoku-Handoutai Seiriyuseisetsugouno Seihou - Google Patents
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JPS5845832B2 - Kinzoku-Handoutai Seiriyuseisetsugouno Seihou - Google Patents

Kinzoku-Handoutai Seiriyuseisetsugouno Seihou

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Publication number
JPS5845832B2
JPS5845832B2 JP50103288A JP10328875A JPS5845832B2 JP S5845832 B2 JPS5845832 B2 JP S5845832B2 JP 50103288 A JP50103288 A JP 50103288A JP 10328875 A JP10328875 A JP 10328875A JP S5845832 B2 JPS5845832 B2 JP S5845832B2
Authority
JP
Japan
Prior art keywords
platinum
gaas
gallium arsenide
arsenide
gallium
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP50103288A
Other languages
Japanese (ja)
Other versions
JPS5227270A (en
Inventor
雄二 奥戸
寿 水村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP50103288A priority Critical patent/JPS5845832B2/en
Publication of JPS5227270A publication Critical patent/JPS5227270A/en
Publication of JPS5845832B2 publication Critical patent/JPS5845832B2/en
Expired legal-status Critical Current

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  • Electrodes Of Semiconductors (AREA)
  • Junction Field-Effect Transistors (AREA)

Description

【発明の詳細な説明】 本発明は砒化ガリウム(GaAs)と白金(Pt)の合
金反応を用いた安定で高品質な金属−半導体整流性接合
を再現性良く製造する方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a stable and high quality metal-semiconductor rectifying junction with good reproducibility using an alloy reaction of gallium arsenide (GaAs) and platinum (Pt).

従来n型砒化ガリウムの上に金属白金を付着して得られ
る整流性接合はそのバリア・ハイド(Barrier
Height )の高いために良く用いられているが、
その信頼性に関して種々の欠点のあることが知られてい
る。
Conventionally, the rectifying junction obtained by depositing metallic platinum on n-type gallium arsenide has a barrier
It is often used because of its high Height), but
It is known that there are various drawbacks regarding its reliability.

特に使用中に接合部が高温になり易い電力用素子に関し
ては動作中に白金と砒化ガリウムの間で合金化反応が進
行し特性の変化がおこったり、また白金の上に他の金属
例えば金(Au)等が付着してあれば白金と砒化ガリウ
ムの反応のみならず上層の金が白金層を通り抜けて砒化
ガリウムに到り素子特性の変化をもたらすこと等の難点
があった。
Particularly for power devices whose joints tend to reach high temperatures during use, an alloying reaction between platinum and gallium arsenide may occur during operation, resulting in changes in properties, or other metals such as gold ( If gold (Au) or the like is attached, there are problems such as not only a reaction between platinum and gallium arsenide but also the fact that the gold in the upper layer passes through the platinum layer and reaches gallium arsenide, causing a change in device characteristics.

本願出願前に頒布された特公昭50−24189号公報
(以下引用例(1)と略称する)にはn型G a A
s結晶表面にpt層を形成し、熱処理してPiとGaA
sの合金層を設けてショットキ障壁を形成させることが
記載されている。
In Japanese Patent Publication No. 50-24189 (hereinafter referred to as Cited Example (1)), which was distributed before the application of the present application, n-type G a A
A PT layer is formed on the surface of the s crystal and heat treated to form Pi and GaA.
It is described that a Schottky barrier is formed by providing an alloy layer of S.

また本願出願日前に出願され、本願出願後に出願公開さ
れた特開昭50−108878号公報(以下引用例(2
)と略称する)には、n型GaAs結晶を加熱しながら
その表面にPt、W(あるいはMo)をこの順に真空蒸
着する方法が記載されている。
In addition, JP-A-50-108878, which was filed before the filing date of the present application and published after the filing date of the present application (hereinafter referred to as (2)
) describes a method of vacuum-depositing Pt and W (or Mo) in this order on the surface of an n-type GaAs crystal while heating it.

引用例(1)は本願と比べて表面にWを付着していない
点が構成上の相違点である。
The difference in structure between the cited example (1) and the present application is that W is not attached to the surface.

実際のデバイスでは合金層の上にAuなとの電極を付け
て動作させる。
In actual devices, electrodes such as Au are attached on top of the alloy layer for operation.

Auと合金層の間(こWがないと動作による温度の上昇
のためAuが合金層を通過してGaAsに至り、素子特
性を変化させてしまう。
Between Au and the alloy layer (without W, Au passes through the alloy layer and reaches GaAs due to the temperature increase due to operation, changing the device characteristics.

また同時に前記温度上昇によってGaが系外へ抜けてし
まう。
At the same time, Ga escapes from the system due to the temperature rise.

このGaの不足を補うためGaAsからGaが供給され
る。
Ga is supplied from GaAs to compensate for this shortage of Ga.

するとPtAs、、とGaAsの界面の位置が変わって
しまう。
Then, the position of the interface between PtAs and GaAs changes.

インバットダイオードのような、界面の下の不純物プロ
ファイルを厳密に設計しなければならないデバイスでは
その電気的特性が劣化してしまう。
In devices such as invat diodes, where the impurity profile below the interface must be precisely designed, the electrical characteristics deteriorate.

引用例(1)の明細書第2頁及び添付図面第3図にショ
ットキ障壁型ダイオードの特性は良好であり信頼性テス
トで耐圧の劣化がなかったと記載されているが、更に高
温あるいは更に長時間の信頼性テストでは前記Gaの抜
は等の理由から特性が劣化してしまうのである。
It is stated on page 2 of the specification and attached drawing Figure 3 of Cited Example (1) that the characteristics of the Schottky barrier diode were good and that there was no deterioration in breakdown voltage in the reliability test, but if In the reliability test, the characteristics deteriorate due to the above-mentioned omission of Ga.

引用例(2)では表面にWを付着せしめる前に熱処理を
行っている点が本願と相違する点である。
Reference example (2) differs from the present application in that heat treatment is performed before attaching W to the surface.

つまり引用例(2)ではGaAsの結晶を加熱しておい
てPtを付着せしめることによりGaAsとPtを反応
させ、その後W、Mo等を付着させ、W2MOを電極等
に使用する金属(例えばAuなど)と、白金と反応した
G a A sとの反応のバリヤーとしているにすぎな
い。
In other words, in the cited example (2), GaAs and Pt are reacted by heating the GaAs crystal and depositing Pt, and then W, Mo, etc. are deposited, and W2MO is used for metals used for electrodes (e.g. Au, etc.). ) and GaAs reacted with platinum.

この場合我々の実験で見たように反応の過程で反応にあ
ずかったGaAsのうちのGaの一部が系外に消失して
、厳密な意味でのPtGa/PtAs2/GaAsとい
う層構造が成立しない。
In this case, as we saw in our experiments, part of the Ga in the GaAs that participated in the reaction disappears out of the system during the reaction process, and the layer structure of PtGa/PtAs2/GaAs in the strict sense is not established. .

更に詳細に述べれば以下のようになる。引用例(2)の
実施例1ではGaAs結晶の上に通常の真空蒸着法を用
いてPtをわずか10大しか蒸着していない。
More detailed description is as follows. In Example 1 of Cited Example (2), only 10 times more Pt was deposited on the GaAs crystal using a normal vacuum deposition method.

これだけ薄いとptは完全な膜にはならない。If it is this thin, PT will not form a perfect film.

従ってその上に形成するMoが直接GaAsと接触して
しまう。
Therefore, Mo formed thereon comes into direct contact with GaAs.

従って良好なショットキバリアが形成できない。Therefore, a good Schottky barrier cannot be formed.

つまりこの実施例1は実現性がないと思われる。In other words, it seems that this first embodiment is not practical.

次に引用伊斡)の実施例2について述べる。Next, Example 2 of the cited work by Isa will be described.

GaAsの結晶を300℃で加熱しなからPtを付着さ
せると、Gaが系外へ抜けていくためPtGaだけでな
(P t5G 33等のGaが不足した相がPtGaと
混ざりあって形成される。
If Pt is attached to a GaAs crystal without heating it at 300°C, Ga will escape from the system, so it will not be just PtGa (Pt5G 33 etc., a phase lacking in Ga will be mixed with PtGa and formed). .

このあとWを上に付着している。After this, W was attached on top.

そのWの付着中P’ t 5 G a 3がPtGaに
なろうとして、GaAsからGaを吸いだすため、その
分だけAsがPtAs2中で過剰になり、厳密なPtA
s2にならず、As過剰の相(ここではPtAs2*と
書く)になる。
During the deposition of W, P' t 5 Ga 3 tries to become PtGa and sucks out Ga from GaAs, so As becomes excessive in PtAs2, and the strict PtA
It does not become s2, but becomes an As-excess phase (herein written as PtAs2*).

しかもPtAs2とPtGa(Pt5Ga3)がはっき
り層として分かれず混合した状態になる。
Moreover, PtAs2 and PtGa (Pt5Ga3) are not clearly separated as layers, but are in a mixed state.

このあとAuを形成し最後OこPtとGaAsを完全に
反応させるためと称して450′C1H2,5分の熱処
理を行なっている。
Thereafter, a heat treatment of 450'C1H2 for 5 minutes was performed to form Au and finally to completely react Pt and GaAs.

しかしこのときでもAsが過剰であることtこ変わりは
ないからPtGa/PtAs2/GaAsという層構造
にはならない。
However, even in this case, there is still an excess of As, so the layer structure of PtGa/PtAs2/GaAs cannot be obtained.

その結果ダイオードとして形成しても、長時間の動作時
においては動作中の温度上昇のため、P t A 52
*とGaAsの界面が除々に反応しP t A 52
*がPtAs2ζこなろうとしてAsが移動する。
As a result, even if formed as a diode, P t A 52
The interface between * and GaAs gradually reacts, resulting in P t A 52
As * tries to become PtAs2ζ, As moves.

しかしWが存在することによってAsは系外へ抜けだせ
ないため厳密な意味でのP t A s2にはなりにく
い。
However, since As cannot escape from the system due to the presence of W, it is difficult to form P t A s2 in the strict sense.

結局実施例2の方法では安定なP t G a/P t
A s2/GaAsという層構造を作れない。
In the end, the method of Example 2 results in stable P t Ga/P t
A layered structure called s2/GaAs cannot be created.

その結果ショットキバリアダイオードを長時間動作させ
るとそのバリアバイトやダイオードのn値が劣化してし
まう。
As a result, when a Schottky barrier diode is operated for a long time, its barrier bite and n value of the diode deteriorate.

本発明の目的は上記の欠点を除去し高温度で動作させて
も安定であるような構造の金属−半導体整流性接合を製
作する方法を提供することである0 本発明によればn型砒化ガリウム(n−GaAs)の上
に500X以上3000X以下の厚さの白金(Pi)を
付着し、さらにその上に500X以上5000A以下の
厚さのタングステン(W)を付着し、全体を熱処理する
ことにより白金層を基板砒化ガリウムの一部分と完全に
反応させて砒化ガノウムー白金砒素−白金ガリウムータ
ングステン(GaAs/PtAs2/PtGa/W)な
る構造に変化させたことを特徴とする金属−半導体整流
接合の製造方法が得られる。
It is an object of the present invention to eliminate the above-mentioned drawbacks and to provide a method for producing metal-semiconductor rectifying junctions of a structure that is stable even when operated at high temperatures. Platinum (Pi) with a thickness of 500X or more and 3000X or less is deposited on gallium (n-GaAs), and tungsten (W) with a thickness of 500X or more and 5000A or less is further deposited on top of that, and the whole is heat treated. A metal-semiconductor rectifying junction characterized in that the platinum layer is completely reacted with a part of the gallium arsenide substrate to change the structure to gallium arsenide-platinum arsenide-platinum gallium-tungsten (GaAs/PtAs2/PtGa/W). A manufacturing method is obtained.

前記本発明(こよれば安定で高品質な整流性接合が得ら
れる。
According to the present invention, a stable and high quality rectifying joint can be obtained.

すなわち、砒化ガリウムと白金砒素の接触は0.9eV
程度の高い電位障壁を持ち、さらに砒化ガリウムおよび
白金砒素は各々金属学的に安定な化合物であり、その二
つを共存させても700’C程度の温度で熱しても反応
はおこらない。
In other words, the contact between gallium arsenide and platinum arsenide is 0.9 eV.
Gallium arsenide and platinum arsenide each have a high potential barrier and are metallurgically stable compounds, so even if they are allowed to coexist, no reaction will occur even if they are heated to a temperature of about 700'C.

また、白金砒素と白金ガリウムも共存させても同様の条
件で反応はおこらず白金ガリウム自身も安定な化合物で
ある。
In addition, even if platinum arsenide and platinum gallium are coexisting, no reaction occurs under similar conditions, and platinum gallium itself is a stable compound.

次にタングステンは高温でも安定な金属であり、白金ガ
リウムや白金、金、其の他と共存させても同様な条件下
では反応を起こすことはない。
Second, tungsten is a metal that is stable even at high temperatures, and even if it coexists with platinum gallium, platinum, gold, or others, it will not react under similar conditions.

従って熱的に極めて安定な金属−半導体整流接合が得ら
れる。
Therefore, a thermally extremely stable metal-semiconductor rectifying junction is obtained.

以下本発明について一実施例を用いて詳述する。The present invention will be described in detail below using an example.

通常の従来方法で前処理されたn型砒化ガリウムの試料
片に一般の真空蒸着法で白金とタングステンを各々50
0Xおよび1000Xの厚さに付着させる。
50% each of platinum and tungsten was deposited using a general vacuum evaporation method on a sample piece of n-type gallium arsenide that had been pretreated using a conventional method.
Deposit to 0X and 1000X thickness.

次にこの試料片を水素雰囲気中で450℃10分間の熱
処理を行ない整流性接合を作る。
Next, this sample piece is heat treated at 450° C. for 10 minutes in a hydrogen atmosphere to form a rectifying junction.

その後試料片の裏面に金ゲルマニウム(AuGe)を約
1000X付着し水素雰囲気中で450℃1分間の熱処
理を行なって抵抗性接触を作る。
Thereafter, about 1000X of gold germanium (AuGe) is attached to the back surface of the sample piece, and a resistive contact is made by heat treatment at 450° C. for 1 minute in a hydrogen atmosphere.

こうして得られた試料片を適当な大きさに切断して化学
研磨(Chemical Etching )を行ない
整流性素子(Diode )を完成する。
The thus obtained sample piece is cut into an appropriate size and chemically etched to complete a rectifying element (diode).

このようにして得られた素子は非常に安定であり、たと
えば500℃で200時間の高温保管を行なっても特性
の変化が認められず従来の方法で得られる接合素子に比
べてはるかに優れた耐熱性を持つことかたしかめられた
The devices obtained in this way are extremely stable; for example, even after high-temperature storage at 500°C for 200 hours, no change in properties was observed, making them far superior to bonded devices obtained by conventional methods. It was confirmed that it was heat resistant.

ここに白金並びにタングステンの厚さの制御が極めて重
要である。
Controlling the thickness of platinum and tungsten is extremely important here.

すなわち余りうすい場合はいわゆるピンホール(Pin
hole )ができる可能性があり、また逆に余りあ
つすぎると基板層、反応物の層、タングステン層等の熱
膨張率の差のために素子に大きなストレス(5tres
s )がかかり、場合によって合金層等がはがれたりし
て素子が破損してしまうこともある。
In other words, if it is too faint, it may be a so-called pinhole.
On the other hand, if the temperature is too high, a large stress (5 tres
s), and in some cases, the alloy layer etc. may peel off and the element may be damaged.

また、このようなことがおこらない場合にも内部ストレ
スのために素子の電気的特性が劣化する。
Furthermore, even if this does not occur, the electrical characteristics of the element deteriorate due to internal stress.

以上本発明を実施例を用いて説明したが、白金およびタ
ングステンの厚さは特許請求の範囲に示した範囲で任意
であり、熱処理温度、時間等は白金の厚さに応じて適宜
決定することにより安定な接合を得ることができる。
Although the present invention has been described above using examples, the thickness of platinum and tungsten is arbitrary within the range shown in the claims, and the heat treatment temperature, time, etc. can be determined as appropriate depending on the thickness of platinum. A more stable bond can be obtained.

Claims (1)

【特許請求の範囲】[Claims] 1 n型砒化ガリウム(GaAs)の表面に500X以
上3000X以下の厚さの白金(Pt)を付着し、さら
にその上に500X以上5oooX以下の厚さのタング
ステン(W)を付着し全体を熱処理することにより白金
層を砒化ガリウムの一部と完全に反応させて、砒化ガリ
ウム−白金砒素−白金ガリウム−タングステン(GaA
s/PtAs2P t Ga −W )なる構造にする
ことを特徴とする金属−半導体整流性接合の製法。
1 Platinum (Pt) with a thickness of 500X or more and 3000X or less is attached to the surface of n-type gallium arsenide (GaAs), and tungsten (W) with a thickness of 500X or more and 5oooX or less is further attached on top of it, and the whole is heat-treated. By this, the platinum layer is completely reacted with a part of the gallium arsenide to form gallium arsenide-platinum arsenide-platinum gallium-tungsten (GaA
A method for manufacturing a metal-semiconductor rectifying junction, characterized by forming a structure such as s/PtAs2PtGa-W).
JP50103288A 1975-08-26 1975-08-26 Kinzoku-Handoutai Seiriyuseisetsugouno Seihou Expired JPS5845832B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP50103288A JPS5845832B2 (en) 1975-08-26 1975-08-26 Kinzoku-Handoutai Seiriyuseisetsugouno Seihou

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP50103288A JPS5845832B2 (en) 1975-08-26 1975-08-26 Kinzoku-Handoutai Seiriyuseisetsugouno Seihou

Publications (2)

Publication Number Publication Date
JPS5227270A JPS5227270A (en) 1977-03-01
JPS5845832B2 true JPS5845832B2 (en) 1983-10-12

Family

ID=14350110

Family Applications (1)

Application Number Title Priority Date Filing Date
JP50103288A Expired JPS5845832B2 (en) 1975-08-26 1975-08-26 Kinzoku-Handoutai Seiriyuseisetsugouno Seihou

Country Status (1)

Country Link
JP (1) JPS5845832B2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4197551A (en) * 1977-09-14 1980-04-08 Raytheon Company Semiconductor device having improved Schottky-barrier junction
JPS5742171A (en) * 1980-08-27 1982-03-09 Matsushita Electric Ind Co Ltd Production of field effect semiconductor device
JPS60219765A (en) * 1984-04-16 1985-11-02 Mitsubishi Electric Corp Schottky barrier electrode

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5024189A (en) * 1973-07-02 1975-03-15
JPS50108878A (en) * 1974-02-01 1975-08-27

Also Published As

Publication number Publication date
JPS5227270A (en) 1977-03-01

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