JPS5846171B2 - Manufacturing method of semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a dielectric isolation substrate used in manufacturing a high voltage complementary semiconductor device.

A dielectric isolation method has been used for some time when manufacturing a complementary semiconductor device that includes both NPN type and PNP type elements within the same semiconductor substrate.

FIG. 1 is a sectional view of a main part showing the dielectric separation method in order of steps, and shows an example using an N-type substrate.

First, as shown in FIG. 1A, a P-type impurity such as boron (B) is selectively introduced into a predetermined area of the entire surface of an N-type silicon substrate 1 with a surface orientation of 100 by ion implantation or the like to form a boron-introduced layer. form 2.

Next, as shown in the figure, the introduced boron (B)
is diffused to form an island-like P-shaped head region 2'.

Then, as shown in FIG. A plateau-like N-type region 4 is formed.

The etching depth is set so that the bottom surface of the removed recess is deeper than the bottom surface of the P-shaped head region 2'.

Then, after selectively diffusing boron (B) on the surface of the P-type head region 3 and arsenic (As) or waste P on the surface of the N-type region 4 to form a P+ layer 5 and an N+ layer 6, A silicon dioxide (Si02) layer 1 is formed on the surface.

Next, as shown in Figure d, a thick polycrystalline silicon layer 8 is formed on the SiO2 layer γ.

Next, the other main surface 9 side of the silicon substrate 1 is polished and removed, and as shown in FIG.
A P-type head region 3' and an N-type region 4', which are insulated and isolated by the 02 layer 1 and formed into island shapes, are obtained.

Note that FIG. 1e is drawn upside down from the above-mentioned figures a to d.

P-type head region 3 of the silicon substrate 10 obtained in this way
' and N-type region 4', respectively, a PNP type element and an NPN
A complementary type semiconductor device is manufactured by forming a type element, and in order to form a high breakdown voltage element, the P type region 3' and the N type element are formed.
The mold region 4' must be deep and the impurity concentration must be low.

In the above example, it is very difficult to make the P-type head region 3' formed using the diffusion method low in concentration and deep, and therefore, such a conventional method is not suitable for dielectric isolation substrates for complementary high voltage semiconductor devices. It was not suitable for production.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a dielectric isolation substrate in which low concentration and deep island-like regions can be easily formed.

The feature of the method for manufacturing a semiconductor device of the present invention is that the entire surface of a P-type (or N-type) semiconductor substrate is selectively removed.
Step 1: Forming an N-type (P-type) plateau-like convex portion on the main surface by epitaxial growth; and Forming a dielectric layer over the entire main surface. forming a polycrystalline semiconductor layer on the dielectric layer; and polishing the other main surface of the semiconductor substrate to expose the bottom surfaces of the P-type and N-type protrusions. It is in.

An embodiment of the present invention will be described below with reference to FIG.

FIG. 2 is a sectional view of a main part showing an embodiment of the present invention in the order of steps, and an example in which a dielectric isolation substrate is manufactured using a P-type silicon substrate 1 will be described.

In the figure a, 1 is a P-type silicon substrate with a surface orientation of 100, and first, the entire surface of the silicon substrate 1 is selectively removed using an anisotropic etching solution using potassium hydroxide (KOH) or the like. A plateau-like convex portion 11 is formed.

The thickness of this convex portion is determined to be a necessary dimension in view of the breakdown voltage and other characteristics of the semiconductor device to be manufactured.

Next, a P type impurity such as poron is introduced into the surface layer of the convex portion 11 by ion implantation to form a P+ layer 12.

It is desirable that the P+ layer 12 be formed only on the surface of the convex portion 12, but if there is no adverse effect in subsequent steps, the P+ layer 12 may be formed on the entire surface of the substrate 1.
It is also possible to form this.

A first dielectric layer, such as a silicon dioxide (Si02) film 13, is then selectively formed over the entire surface of the substrate 1.

An opening 14 is provided in this S io 2 film 13 at a position where an N-type convex portion is to be formed in a subsequent step.

Next, as shown in the figure, N is grown in the opening 15 by epitaxial growth on the whole surface of the substrate 1.
-Grow a -type epitaxial layer.

At this time, a first polycrystalline silicon layer 15' is formed on the S t 02 layer 13.

Next, as shown in FIG.
5' and an unnecessary portion of the N-type epitaxial layer 15 are selectively removed to form an N-type plateau-like convex portion 16.

In order to set the thickness of the convex portion 16 to a desired dimension, the thickness of the above-mentioned epitaxial layer 15 may be controlled.

Next, an N-type impurity such as arsenic (As) or waste is introduced into the surface layer of the convex portion 16 to form an N+ layer 1T, and the surface of the convex portion 16 is further oxidized to deposit the SiO2 film 18. A second dielectric layer 18 is formed.

At this time, after completely removing the first S r 02 film 13, a second S io 2 film is deposited on the metal surface of the substrate 1.
A film 18 may also be formed.

Next, as shown in FIG. 4D, a second polycrystalline silicon layer 19 is grown on the second SiO2 film 18.

Thereafter, the other main surface of the substrate (the back surface of the substrate) is removed by a polishing method to expose the bottom surfaces of the P-type and N-type protrusions 11 and 16 that can protrude into the second polycrystalline silicon layer 19. .

Note that e in the figure is drawn upside down from a''-d.

In this way, the dielectric isolation substrate 10 is provided with the P-type and N-type island regions 11' and 16' separated from each other by the dielectric layer with their surfaces exposed in the polycrystalline silicon layer 18. can get.

As is already clear from the above description, the impurity concentration and thickness of the P-type and N-type island regions 11' and 16' can be controlled to desired values.

That is, the impurity concentration is determined by controlling the impurity concentrations of the P-type silicon substrate 1 and the N-type epitaxial layer 15, and the thickness is determined by controlling the thickness of the P-type convex portion 11 explained with reference to FIG. The amount of directional etching is shown in the same figure.

They can be determined independently by controlling the thickness of the N-type epitaxial layer 15 and the thickness of the N-type convex portion 16 as explained in FIG. is possible.

It will be easily understood that the present invention can be practiced by reversing all the P-type and N-type in the above description.

Further, the first and second dielectric layers 13 and 18 are S io 2
The material is not limited to a film, and may be any commonly used dielectric material.

As explained above, the dielectric isolation substrate obtained according to the present invention has P-type and N-type island regions having desired impurity concentrations and thicknesses, so that it is possible to manufacture a high breakdown voltage complementary semiconductor device.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of a main part used to explain a conventional method for manufacturing a dielectric isolation substrate, and FIG. 2 is a cross-sectional view showing an example of an improved method for manufacturing a dielectric isolation substrate, which is the main part of the present invention. FIG. 1... Semiconductor substrate having a conductivity type, 10...
... Dielectric separation substrate, 11 ... One conductivity type convex portion, 12 ... One conductivity type impurity introduction layer, 13.18
...First and second dielectric layers, 14...
・Opening portion, 15...Reverse conductivity type epitaxial growth layer, 16...Reverse conductivity type convex portion, 17...
- Opposite conductivity type impurity introduction layer, 19... second polycrystalline semiconductor device

Claims (1)

[Claims] 1 In this case of a dielectric isolation substrate having T-type and P-type island regions insulated from other regions by a dielectric layer, P
a step of selectively removing one surface of a P-type (or N-type) semiconductor substrate to form a P-type (N-type) plateau-like protrusion in a P-type (N-type) island-like region; A first opening having an N-type (P-type) island-like region forming portion on the entire surface of the semiconductor substrate including the surface of the semiconductor substrate.
A step of forming a dielectric layer and growing an N-type (P-type) semiconductor layer on the main surface to form an N-type (P-type) single crystal layer and a forming a first polycrystalline semiconductor layer on the first dielectric layer; removing the first polycrystalline semiconductor layer and forming the N-type (P-type) single crystal layer in a plateau-like convex portion; forming a second dielectric layer on both surfaces of the semiconductor substrate including the N-type (P-type) convex surface; and forming a second polycrystalline semiconductor layer on the second dielectric layer. and polishing the other main surface of the semiconductor substrate to expose the bottom surfaces of the P-type and N-type plateau-like protrusions that protrude into the second polycrystalline semiconductor layer. 1. A method for manufacturing a semiconductor device, comprising the step of forming a semiconductor device.