JPS5846637B2 - central control lock - Google Patents

Description

[Detailed description of the invention] The present invention locks each of a plurality of controlled devices.

By giving an unlocking key number and using a selection switch that allows locking and unlocking signals to pass to only one of the controlled devices, it is possible to lock and unlock multiple controlled devices from two locations. This invention relates to a centrally controlled side lock that performs locking.

The present invention will be explained in detail below.

In FIG. 1, A is a keyboard, and there are 10 switches corresponding to numbers O to 91. When a key with a corresponding number is pressed, the hot line corresponding to that number is grounded.

B is an encoder which sorts error numbers and correct numbers and has n outputs for n controlled devices.

C and E are changeover switches that are interlocked with each other and are used to control n controlled devices.When the key number is 4 digits, these changeover switches C and E have terminals corresponding to the respective digits and terminals for error numbers. It requires one terminal and one terminal for the flip-flop for setting the relay and determining the reset.
This is a switch with 6 circuits and n contacts for n controlled devices.

D is the main body of the lock device, the structure and function of which will be described later.

F is a set/reset discrimination circuit, which drives the relay 1 drive circuit G.

Oh, this set. The reset determination circuit F is inverted in response to a negative pulse generated when the keyboard A is operated with the correct key number on the lock device body.

G is a relay drive circuit in which a relay driven by a transistor controls a controlled device.

Next, a block diagram of the main body of the locking device shown in FIG. 2 will be described.

21 is an operation pulse generation circuit, 22 is a set pulse generation circuit, and 23 is an operation pulse blocking circuit.This operation pulse blocking circuit 23 is supplied with a part of the set pulse signal in the set pulse generation circuit 22, and is also used for generating operation pulses. The operating pulses of the circuit 21 are supplied.

24 is a simultaneous pulse blocking circuit, 25 is a key number storage circuit, 2
6 is a key number storage discrimination circuit; 27 is a key number order discrimination circuit;
28 is a reset gate circuit, 29 is an automatic erase circuit, 30
is an initial condition determining circuit, and this automatic erasing circuit 29 erases the key number stored in the key number storage circuit 25 and at the same time shuts off the operation pulse generating circuit 21.

31 is a reset trigger generation circuit, 32 is a set/reset discrimination drive circuit, and 33 is a switch output circuit, and the output of this switch output circuit 33 operates a load 34 such as a lock.

When the power is turned on using the circuit configuration described above, the initial condition determining circuit 30 is activated.

This operation of the initial condition determination circuit 30 drives the reset/trigger generation circuit 31, which then operates the switch output circuit 33 via the set/reset determination drive circuit 32, which drives the load 34 to solve the initial condition. Do the lock.

Next, when locking the door, the user drives the set pulse generation circuit 22 to generate a set pulse.

One of the set pulses drives a switch output circuit 33 via a set/reset discrimination drive circuit 32 to lock a load 34 such as a lock.

At the same time, the other set pulse is applied to the operating pulse blocking circuit 23 and releases the operating pulse blocking circuit 23.

If you want to unlock the door again, press the OZ operation pulse generation circuit 21.
to generate operating pulses.

This operation pulse passes through the operation pulse blocking circuit 23, which is released when the lock is locked, and is applied to the key number storage circuit 25 via the simultaneous pulse blocking circuit 24, where the key number is stored and the key number memory determination is performed. applying a pulse to circuit 26;
This key number memory determination circuit 26 detects whether the operation pulse is a designated number or not.

If it is the specified number, the key number memory determination circuit 26
A pulse is applied to the key number order determining circuit 27, and the key number order determining circuit 27 detects whether or not it is in the designated order.

If it is in the specified order, the key number order determining circuit 2
7 and a pulse is applied to the reset gate circuit 28.

In this way, when specified input signals are applied in a specified order, the reset gate circuit 28 opens, and the reset trigger generation circuit 31 and set.

Each of the signals passes through a reset determination drive circuit 32, drives a switch output circuit 33, and is unlocked.

Next, the case of erroneous operation will be explained.

When the operation pulse generating circuit 21 generates an operation pulse with a number other than the specified number, this erroneous operation pulse passes through the operation pulse blocking circuit 23, the simultaneous pulse blocking circuit 24, and the key number storage circuit 25, and The signal is applied to the number storage discrimination circuit 26.

The key number memory determination circuit 26 detects an erroneous pulse and applies the erroneous pulse to the automatic erasing circuit 29, thereby driving the automatic erasing circuit 29.

The erroneous pulse applied to the automatic erasing circuit 29 is applied to the key number storage circuit 25 button and the operation pulse blocking circuit 23, erasing the key number stored in the key number storage circuit 25, and also erasing the key number stored in the key number storage circuit 25. cut off.

Since re-operation is not possible in this residue 1 state, by driving the set pulse generation circuit 22, the operation pulse blocking circuit 23 is released and re-operation becomes possible.

Next, when the operation pulse generation circuit 21 generates operation pulses in an order other than the specified order, this erroneous operation pulse is applied to the key number order determination circuit 27.

Then, the key number order determining circuit 27 detects an erroneous pulse and applies the erroneous pulse to the automatic erasing circuit 29 to perform the same operation as described above.

Also, when multiple operation pulses are set,
When a plurality of operation pulses are generated simultaneously, the simultaneous pulse blocking circuit 24 is activated and the key number storage circuit 25 is fixed.

Therefore, the key number storage circuit 25 becomes inoperable, and due to the inoperability of the key number storage circuit 25, no operation pulse is applied to the circuits after the key number storage discrimination circuit 26.

In this case, by removing the plurality of simultaneously operated operation pulses, the simultaneous pulse blocking circuit 24 is automatically released and the operation can be performed again.

As described above, if a malfunction occurs, unlocking is prevented by the operation pulse blocking circuit 23, simultaneous pulse blocking circuit 24, key number memory discrimination circuit 26, key number order discrimination circuit 27, etc., and the correct operation is performed. The lock will only be unlocked when the

Here, the block diagram shown in FIG. 1 will be explained in detail.

If you operate keyboard A to lock or unlock one of the multiple controlled devices and leave all the memory, you can lock or unlock the remaining controlled devices. Since it is not possible to do so, it is necessary to manually erase all memory.

For this reason, a delayed clear circuit H is provided.

Next, the operation will be described based on FIGS. 3, 4, 5, and 6.

When keyboard A is operated with the correct key number, diodes D12 to D15 and transistor TR1 in the lock device body are activated.
An AND output is output from a four-man power AND circuit constituted by the following, and the collector potential of the transistor TR□ is lowered.

At that moment, the monostable multivibrator circuit MM1 of the delayed clear circuit H starts operating.

If the operating time of this monostable multivibrator circuit MM is set to TR seconds as shown in FIG. Operate.

At that moment transistor TR2 and diodes D1-D
An OR output is output from the OR circuit constituted by , and the collector potential of the transistor TR2 is lowered to the ground potential, thereby erasing the memories in the flip-flop circuits FF6 to FF81 of the set/reset discrimination circuit F.

6, the transistor TR1, the monostable multivibrator circuit MM09MM2, and the transistor T
The output waveforms of R2 are shown in the above order.

The output terminals of the flip-flop circuits FF2 to FF are 4
Since it is connected to the manual AND circuit, the collector potential of the transistor TR1 rises above the ground potential at the same time as the memory is erased.

Therefore, transistor TR1 is turned on for Ta seconds,
Return to original state.

Next, the operation when opening and unlocking relay RL1 of relay drive circuit G will be explained.

Set the interlocked changeover switch C to the switch SW1 position.

A circuit of an encoder B corresponding to key number 1974, for example, is connected to terminals IP to 4P of switch SW1 of changeover switch C.

That is, when opening and releasing relay RL1, flip-flop circuits FF2 to FF are switched from clip-flop circuit FF2 to flip-flop circuit FF3 to flip-flop circuit FF4 to flip-flop circuit FF,
You must set them in this order.

In FIG. 3, since the key number of relay RL1 is set to 1974, the terminal IP of switch SW1 corresponding to key number 1 of encoder B is connected to flip-flop circuit F.
The terminal 2P of the switch SW1 corresponding to the key number 9 of the encoder B is connected to the set terminal T2 of F2, and the terminal 3P of the switch SW□ corresponding to the key number 7 of the encoder B is connected to the set terminal T3 of the flip-flop circuit FF3. - The terminal 4P of the switch SW1 corresponding to the key number 4 of the encoder B is connected to the set terminal T4 of the flip-flop circuit FF4.

Therefore, the terminals Err of the switch SW1 corresponding to the remaining numbers 2, 3, 5, 6, 8, and 0 are connected to the set terminal T1 of the flip-flop circuit FF1.

D19~D25 t D26~Dst t D32~D
37 is switch SW1. SW2. This is a diode connected to the terminal Err of SW3.

Switch SW2 of changeover switches C and E. SW also uses the key number 2817 in the same manner as switch SW1.
and 4290.

Therefore, by switching the changeover switches C and E, a plurality of controlled devices can be locked and unlocked, respectively.

Note that in the main body of the lock device, D6 to Dll are diodes, TR3 is a transistor, and in the relay 1 drive circuit G, RL2. RL, is switch SW2
．． A relay corresponding to SW3 is shown, TR4 to TR are transistors, and ZD1 to ZD3 are Zener diodes.

In addition, for the set/reset discrimination circuit F, FF6 to F
F8 represents a flip-flop circuit, and D16 to D18 represent diodes.

As described above, the present invention provides a central control lock that can reliably and easily lock and unlock a plurality of controlled devices from two locations.

[Brief explanation of the drawing]

Fig. 1 is an electrical block diagram of a central control lock according to an embodiment of the present invention, Fig. 2 is an electrical block diagram of the main body of the lock device, and Fig. 3 is a wiring diagram of the keyboard, encoder, and selector switch. Figure 4 is a wiring diagram of the changeover switch, lock device body and set, reset discrimination circuit, relay drive circuit and delayed clear circuit, and Figure 5 is an electrical circuit diagram of the lock device body and delayed clear circuit.
FIG. 6 is a diagram showing a partial output waveform of the device of FIG. A: Keyboard, B: Encoder C, E: Selector switch, D: Lock device body, F: Set, reset Discrimination circuit, G
...Relay drive circuit, H...Delayed clear circuit.

Claims (1)

[Scope of Claims] 1. A plurality of operation pulse generation circuits that can be operated from the outside, and a key number that determines whether the pulses generated by the operation pulse generation circuits are correct or not and the order thereof, and inputs the pulses generated in the correct order. Memory discriminating circuit 3 is set by the government number order discriminating circuit and this key number order discriminating circuit. It consists of a switch output circuit connected via a reset discrimination drive circuit, and the center reset discrimination is performed by the output of the key number storage discrimination circuit or the key number order discrimination circuit, and the La isochi output circuit is operated via the drive circuit to unlock the lock. When closing and locking, a plurality of externally operable set pulse generation circuits are operated to generate set pulses, and these set pulses are added to the switch output circuit via the set/reset discrimination drive circuit. A locking device main body is formed to perform locking, and a plurality of controlled devices are connected to the locking device main body via a changeover switch, and by switching the changeover switch, the plurality of controlled devices and
The centralized control device is characterized in that the plurality of operation panels and the plurality of set pulse generation circuits are selected, and the plurality of controlled devices are unlocked and locked with key numbers appropriate for each. Control side lock.