JPS5846732B2 - logic operation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a logic operation circuit, and particularly to a logic operation circuit configured with complementary MO8 transmission gates.

FIG. 1 shows an example of a conventionally known binary full adder circuit using complementary MO8 transmission gates.

In FIG. 1, i is an arbitrary number and indicates a binary full adder circuit for the first digit in a two-digit adder circuit.

1 to 6 are input terminals, and input terminal 1 has lower digits (
A carry signal C1-1 from the i-1 digit) is applied (this is called the 11" carry signal).

Addend and augend signals Aj and Bi are applied to input terminals 2 and 3, and input terminal 4 receives a signal Ni-1 which is an inversion of the carry signal from the lower digit (this is called the O carry signal). is applied.

Input terminal 5 is connected to the low voltage power supply terminal of the circuit and is fixed to the logic value n On state.

The input terminal 6 is connected to a power supply terminal with a desired voltage value and is fixed at a logical value l.

7 to 14 are complementary MO8s in which a P-channel MOS transistor and an N-channel MOS transistor are connected in parallel.
7 and 8 constitute the sum output unit 15 of the addition cycle, 9 and 10 constitute the carry propagation unit 16, and 11 to 14 constitute the carry generation unit 17, respectively. It consists of

18 is a NAND circuit, 19 is an exclusive OR circuit, 20 is a NOR circuit, 21 to 23 are inverter circuits, and 18 to 23 are a sum output section 15 and a carry propagation section 1.
IIJIN circuit 24 that controls 6 and the carry generation section 17.
It consists of

25 to 27 are output terminals, and the sum output Si is the terminal 2.
1 carry signal Ci and O carry signal Ni from 5 to the upper digit are obtained from terminals 26 and 27, respectively.

With this configuration, the calculation time of this full adder circuit (after Ai and Bi are applied to Si.

Ci, Ni) is the sum of the delay time in the control circuit 24 and the delay time in the sum output section 15, or the delay time in the control circuit 24 and the carry propagation section 16 (or the carry generation section). 17) is the sum of the delay time.

Also, a binary n
The digit addition circuit includes a control circuit 24 for each digit and a carry generation section 15.
operate at the same time, the calculation time is the sum of the delay time in the control circuit 24 and the delay time in the carry propagation section 16 (n-1
digit) and the delay time at the sum output section of the n-th digit.However, since the carry propagation section 16 uses a complementary MO8 transmission gate, the signal propagation time is short, so the addition is It was characterized by its ability to speed up calculations.

However, conventionally, no consideration has been given to using this type of full adder circuit in a logic operation circuit section in a data processing device.

That is, in general, the logic operation circuit section of a data processing device performs arithmetic operations (addition, subtraction, etc.) and various logical operations (AND, OR, exclusive OR, etc.) based on the contents of the operation specification section of the instruction. However, it has not been considered in the past to use the full adder circuit shown in FIG. 1 as a logical operation circuit section capable of performing the arithmetic operations and logical operations.

In this case, the problem is how to correspond between performing arithmetic operations and performing other operations.

The present invention performs a wired OR of the output of a binary full adder circuit using a complementary MO8 transmission gate and the output of a signal conversion circuit for performing logical operations, and outputs the logical operation circuit. The feature is that a carry suppression circuit is added to the output section to suppress carry signals during calculation, and its purpose is to maintain the high speed of the binary full adder circuit using complementary MO8 transmission gates. The purpose is to expand its functionality as a logic operation circuit.

FIG. 2 shows an embodiment of the present invention, and 28 is a binary full adder circuit using the complementary MO8 transmission gate shown in FIG.

In the case of the present invention, two-variable A i + B i signals are applied to input terminals 2 and 3, which are subjected to arithmetic and logical operations.

The input terminal 29 is a terminal for applying a state signal M for selecting an arithmetic operation or a logical operation, and 30 is a terminal for applying a selection signal S for determining the type of operation.

Numerals 31 and 32 are NAND circuits, and 33, 36, and 37 are inverter circuits.

The status signal M applied to the input terminal 29 is sent to the NAND circuit 31
and one terminal of 32.

The output of exclusive OR circuit 19 is NAND circuit 3
The output of the inverter circuit 33 is connected to the other input terminal of the NAND circuit 32.

31 to 33 constitute a carry suppression circuit 34.

Inverter circuits 36 and 37 are connected between the gates of the P-channel MOS transistors and N-channel MOS transistors of transmission gates 7 and 8, respectively, and the gates of the N-channel MOS transistors are driven by the outputs of the inverter circuits.

The output of the NAND circuit 31, which is one output of the carry suppression circuit 34, is the P-channel MOS of the transmission gate 7.
It is connected to the gate of the transistor and drives the transmission gate 7.

Similarly, the output of the NAND circuit 32, which is the other output of the carry inhibit circuit, drives the transmission gate 8 by 1.

35 is a signal conversion circuit that performs various logical operations determined by the combination of selection signals S, and its output is wire-ORed at the sum output terminal 25 of the adder circuit.

Next, the operation of this logical operation circuit will be explained.

When the state signal M has a logical value "l", the output of the signal conversion circuit 35 becomes a high impedance state, and the signal conversion circuit 35
is disconnected from the sum output terminal 25.

Therefore, due to the operation of the carry inhibit circuit 34, the circuit shown in FIG. 2 operates as the binary full adder circuit shown in FIG.

Next, when the status signal M is set to ``O'', the two outputs of the carry suppression circuit 34 (the outputs of the NAND circuits 31 and 32) both have the logical value ``X1'', and the transmissions 7 and 8 of the complementary MO8 are turned off. , the binary full adder circuit 28 is separated from the sum output terminal 25.

At the same time, the output of the signal conversion circuit 35 appears at the sum output terminal 25, and various logical operations determined by the combination of the selection signals 30 shown in FIG. 2 are performed.

Therefore, the operation time of this logical operation circuit is 2
This is the sum of the calculation time of the decimal full adder circuit and the delay time of the carry suppression circuit.

As explained above, according to the present invention, the carry suppression circuit is simply added to the binary full adder circuit, so the calculation time is reduced by expanding the function from the binary full adder circuit to the logic operation circuit. The only increase is the delay time of the carry and inhibition circuits, and there is an advantage that a high-speed logic operation circuit can be realized.

For example, in a parallel n-digit logic operation circuit in which an arbitrary number n of these logic operation circuits are connected in cascade, all the carry suppression circuits for each digit operate simultaneously. ) TA is parallel n
It is the sum of the calculation time TB of the digit-by-digit addition circuit and the delay time TO of one carry suppression circuit (TA = TB + Tc), and since TB>Tc, the logic An arithmetic circuit can be realized.

[Brief explanation of drawings]

FIG. 1 is a circuit configuration diagram showing an addition circuit which is the central part of the present invention, and FIG. 2 is a circuit configuration diagram showing an implementation of a logic operation circuit according to the present invention. 1 to 6, 29, 30... Input terminal, 7 to 14.
...Complementary type MO8 transmission gate,
15... Sum output section, 16... Carry propagation section, 17... Carry generation section, 18, 3L32
...NAND circuit, 19...Intrusive OR circuit, 20...NOR circuit, 21-2
3, 33, 36° 37...Inverter circuit, 2
4... Control circuit, 25-27... Output terminal, 28... Binary full adder circuit, 34...
・Carry suppression circuit, 35 songs・Signal conversion circuit.

Claims (1)

[Claims] 1 P-channel MOS transistor and N-channel MOS
Complementary MO8 with a structure in which transistors are connected in parallel
It has a binary full adder circuit that uses a plurality of transmission gates to constitute a carry propagation section, a carry generation section, and a sum output section, and a logic operation circuit that performs a plurality of logic operations. A logic operation circuit that outputs a wired-OR and is further equipped with a carry suppression circuit for suppressing a carry signal during operations other than arithmetic operations.