JPS5846736B2 - Multiprocessor arithmetic control unit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a multiprocessor arithmetic control device whose functions are improved by using a plurality of processors.

In recent years, with the rapid development of semiconductor technology such as LSI and microprocessors, microcontrollers and programmable controllers (hereinafter referred to as PCs) have become popular in control systems.
Devices have been realized that express functions such as (abbreviated as ``)'' using software.

On the other hand, there is an unrelenting demand for higher functionality and improved performance of this type of equipment, such as improved arithmetic execution speed.

Multiplication of processors is considered as a technical method to meet such demands.

In multiprocessing, the calculation control that was executed by one processor is divided and assigned to multiple processors.
By executing these in parallel, the objective function, that is, the execution speed of the program is improved.

Figure 1 is a block diagram showing an example of a conventional multiprocessor arithmetic control device, and in the figure 1a1t1a2...
1an is a processor, 1b1, 1b2, etc.
...1bn is each processor 1 al t 1
a2... is a storage device connected to or included in 1an.

Further, 1c1, 1c2...1cn are input/output interfaces connected to or included in the respective processors 1a1, 1a2...1an, 2 is a common storage device, and 3 is a common data bus. .

In a multiprocessor arithmetic control device having such a configuration, each processor 1a] l 1 a2...1
an is the storage device 1b that is owned or installed, respectively.
1, 1b2... The required functions are performed by executing the programs stored in 1bn.

Each processor 1a1, 1a2 is stored in the common storage device 2.
...Input/output data seen from 1an, that is, input/output signals to the outside, data during calculation, parameters, constants, etc. are stored.

And each processor'al s 1 a2...
- 1an accesses the storage contents of this common storage device 2 at an arbitrary timing determined by the program owned by each processor or the content of data in the common storage device 2, so that each processor 1 al ,
1, a2, . . ., 1an to realize data sharing and data exchange.

However, in such a case, each processor 1a11
The memory cycle time for 1a2...1ao to access data in the common storage device 2 is different from that of each storage device 1b.
1, 1b2...A roughly equivalent memory cycle time of 1bn is required.

Therefore, the amount of data accessed to the common storage device 2 has an upper limit per time.

Furthermore, in order to avoid the inconvenience of multiple processors accessing the common storage device 2 at the same time, it is necessary to provide a complicated and expensive memory access priority control circuit.

In addition, when such a simultaneous access request occurs, while a specific processor is accessing the common storage device 2, other processors must stop executing their programs and wait until that processor itself is allowed access. There is.

Therefore, in the conventional multiprocessor arithmetic and control device,
Its operating speed is limited by the amount of access from each processor to the common storage device 2 and the memory cycle time.

As a result, it has been difficult to increase the number of multiprocessors, or to thereby improve calculation speed, improve functions, etc.

In addition, this makes it difficult to apply the method to programmable controllers, etc., which emphasize response speed to processes, that is, real-time performance.

The present invention has been made in view of the above circumstances, and it is possible to shorten the effective access time to the common storage device of each multi-processor, perform high-speed calculations, and achieve an unprecedented number of multi-compounds for improved functionality. The object of the present invention is to provide a novel multiprocessor arithmetic control device that can perform the following functions.

Hereinafter, one embodiment of the present invention will be described in detail with reference to the block diagram shown in FIG.

In the figure, Pi, P2, P3, . . . , Pn are processor arithmetic and control units, 3 is a common data bus line, and 4 is a signal line for forwarding transmission rights.

In addition, the processor arithmetic control unit PI, P2゜P3...
...Pn are processor sections 1, 1, 2.1, and
3...1.n and an interface section 5.1, 5.2 for coupling between the processors.・・・・・・5・
nFurthermore, external people signal terminal group 6・1,6・2゜...
...6.n is provided.

FIG. 3 is a block diagram showing details of the processor arithmetic and control device, in which numeral 1 indicates the processor section shown in FIG. 2, and numeral 5 indicates the input/output interface section shown in FIG.

The processor section 1 includes a processor 1a, a program storage device 1b, an external interface device 1c, and a data storage device 1d.

In addition, the interface unit 5 includes a transmission right forwarding control circuit 5.
a, a transmission data buffer storage device 5b, a reception data buffer storage device 5, a C% bus driver 5d, and a bus receiver 5e.

Note that 6 is a group of external signal terminals.

Note that the various elements within the processor arithmetic control unit are generally coupled to each other via signal buses.

With such a configuration, the processor 1a executes the program stored in the program storage device 1b.

In the process of executing this program, data storage device 1
The data is read from 1d, the data is referred to, and the calculation specified by the program is performed, and the calculation result is written to the data storage device 1d.

Further, the external interface device 1C interfaces the processor arithmetic control device with the outside, and inputs data from the outside via the external person output signal terminal group 6, and conversely outputs data from the processor arithmetic control device to the outside. Do the following.

External input data is written to data storage device 1d by processor 1a.

Furthermore, data in the data storage device 1d that should be output to the outside is read out by the processor 1a and transferred to the external interface device 1c.

Timings for inputting and outputting these data to the outside and reading and writing data to the data storage device 1d are arbitrarily determined by the program.

By the way, as shown in FIG. 3, when viewed from the processor 1a, the data storage device 1d and the transmission data buffer storage device 5 are
b is connected in parallel with the same connection line for data writing.

Therefore, when the contents of the data storage device 1d are partially updated by the operation of the processor 1a, the updated data is written to the data storage device 1d and simultaneously written to the transmission data buffer storage device 5b.

The data written in the transmission data buffer storage device 5b in this manner is gated to the side leg output S of the transmission right sequential system circuit 5a, and is thereby sequentially transmitted to the common data bus line via the bus driver 5d at a predetermined timing. Output to 3.

The data output to the common data bus 3 is transmitted to each data storage device 1d via the bus receiver 5e and the received data buffer storage device 5C in all the processor arithmetic and control units connected to the common data bus 3.
written to.

Here, the transmission right sequential transmission system circuit 5a has a plurality of transmission data buffer storage devices 5b provided in each processor arithmetic and control unit, and only one transmission data buffer storage device that has obtained the transmission right without entering the transmission state at the same time. This is to control the signal so that it is in the transmitting state.

In this case, for example, as shown in FIG. 2, each interface unit s-i, s-2, 5
・3...5・n are connected in a loop, and the transmission right forwarding side leg circuit 5a sequentially transfers the transmission right in a baton pass manner.

The transmission data buffer storage device 5b, which has obtained the transmission right, stores data of a specified number of words within a specified period of time in a FIFO format.
It is output to the common data bus 3 according to the first-in, first-out principle.

In this case, if all the data in the transmission data buffer storage device cannot be output within a predetermined time, the remaining data will be processed the next time transmission rights are obtained.

Furthermore, if there is no data to be output even after obtaining the transmission right, the transmission right is immediately transferred to the next transmission data buffer storage device 5.
Give it to b.

The storage capacity of the transmission data buffer storage device is appropriately determined in relation to the storage capacity of the data storage device, the operating speed of the processor, the number of data updates per unit time, the data transmission speed of the common data bus, and the like.

Therefore, for example, the transmission data buffer storage device 5b
If the amount of data written from the processor 1a exceeds the output data amount allowed per unit time of the common data bus and the buffer storage capacity is about to overflow, the processor 1a stops the calculation operation and sends Wait for storage space in the buffer storage device to free up.

Therefore, each processor having its own program in the multiprocessor arithmetic control device of the above embodiment physically has its own data storage device, and shares the same data storage device in the information space. .

Then, only the updated data in the 110th cycle and memory cycle of each processor 1a is transferred onto the common data bus 3.

In this way, a significant effect can be obtained compared to the conventional system in which one data storage device is shared by a plurality of processors.

In other words, data in the common data storage device can be updated extremely quickly and smoothly.

Furthermore, the procedure for updating data in the common data storage device is standard and can be realized only by hardware or processor firmware.

Therefore, the operator does not need any intervention from user software and can operate the system without being aware of it.

It should be noted that the present invention is not limited to the above-mentioned embodiments; for example, although the above-mentioned embodiments have mainly been described based on the architecture and algorithm, this embodiment can be implemented in various ways such as hardware, firmware, or software.

As described in detail above, the present invention provides a method for updating data in a plurality of processor arithmetic control devices.
The data is temporarily stored in a transmission data buffer storage device provided in the interface section of the processor arithmetic and control device, and this data is sequentially transmitted to the data storage device of each processor arithmetic and control device under the control of the transmission right forwarding control circuit. This is what I did.

Therefore, it is possible to provide a multiprocessor arithmetic control device that can share data between processors and transmit data at high speed, thereby achieving good real-time response speed to the processes to be controlled. .

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an example of a conventional multiprocessor calculation control device of this type, FIG. 2 is a block diagram showing an embodiment of the present invention, and FIG. 3 is a block diagram showing the processor calculation side of the above embodiment. FIG. 2 is a block diagram of the device. Pl, P2...Pn... Strong processor arithmetic control device, 1.1, 1.2.・・・・・・１・
n...Processor section, 3...Common data bus, 5...Interface section, 1a...
...Processor, 1b...Program storage device, 1c...External interface device, 1
d...Data storage device.

Claims (1)

[Claims] 1. It has a processor section and an interface section, executes a program stored in the storage device of the processor section, controls external equipment via an external interface device, and also controls transmission rights of the interface section.
A plurality of processor arithmetic and control units are provided which transmit data to a common data bus using transmission rights obtained under the control of the circuit, and the input/output data of each processor arithmetic and control unit is stored in a common storage device connected to this common data bus. In such a system, each time data is updated in each processor arithmetic and control unit, the updated data is temporarily stored in a transmission data buffer storage device of the interface section of the processor arithmetic and control unit, and this stored data is transmitted. A multiprocessor arithmetic and control device, characterized in that the data is transmitted to the data storage device of each processor arithmetic and control device via the common data bus line under the control of a sequential transmission system circuit.