JPS5846864B2 - semiconductor memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a dynamic memory device that utilizes the idea of a minority carrier trap for data storage.

A dynamic memory having a structure having a highly doped to lightly doped junction of N-type silicon with a source and drain region separated by a P-type injector region was proposed separately by the applicant; Memories have the problem of low memory packaging density because each pot memory cell requires an external diode as a gate device when forming a two-dimensional memory array.

It is an object of the present invention to provide a memory circuit that does not require external diodes for each memory cell.

Another objective is to integrate the gate device as an integral device element by forming a low-barrier Schottky diode in the drain region to perform the gate function, and to inject minority carriers to avoid the use of external circuit elements. - To provide trap dynamic memory.

According to the present invention, a single device semiconductor dynamic memory is formed with a heavily doped-lowly doped-highly doped N-type junction below a P-type injector region.

These junctions trap injected minority carriers.

Minority carriers are detected by sensing the current between source and drain regions placed on either side of the injector region.

Ohmic contacts are used in the source and injector regions, and a low barrier Schottky contact is formed in the drain region.

A highly doped N-type region is provided to provide isolation between the Schottky contact depletion region and the injector region.

FIG. 1 shows a cross-sectional view of a dynamic memory cell according to the invention.

The substrate 10, typically a P-type silicon substrate, is ]O~20
It is formed to have a resistivity of Ω.

An N-type semiconductor layer 20 is formed on the top surface of the substrate 10, and an N epitaxial layer is grown thereon.

This layer will be added to the area + It is divided into 40.50.

The N-type region 20 is an oxide region 30 that dielectrically isolates the cell.
separated by.

A 400-500X thin oxide layer is thermally grown on top of the N epitaxial layer.

A photoresist mask is used to form an opening in a portion corresponding to region 22.

N region 22 is formed by ion implantation of phosphorus.

The photoresist is then removed and the 8102 layer 60 is deposited.

A typical thickness of layer 60 is on the order of 300 oA.

The N+ region 22 divides the N epitaxial region into two parts 4.
Separate at 0°50.

Openings 62°64.66 are formed in the Si02 layer 60.

Aperture 62 defines an N+ source region 68 and aperture 64 defines a P source region 68.
+injector region 72 and surrounding N+ region 70
There is a rail provided.

A metal wire 7 is provided in the source region 68 and the injector region 72.
4.76 is deposited.

In the N+ region, for example, by ion implantation of phosphorus or arsenic, P
The + region can be formed by boron ion implantation.

Opening 66 corresponds to the drain region.

The feature of the present invention is the N sufficient distance area, that is, the reach-through area 22.
and that there is no N0 region in the drain portion of the epitaxial region 50.

Instead of forming an N+ region in the drain region, the present invention forms an N- epitaxial region 50 and a contacting site train opening 6.
Low barrier Schottky barrier diode (SB
D) Using 80 - A metal line 82 is deposited on top of the diode 80 to form the drain contact.

Low barrier Schottky diodes are formed using titanium, tungsten, alloys of titanium and tungsten, chromium, tantalum, or other metals that have a barrier hide of less than about 0.55 eV relative to N-type silicon. Ru.

The metallization to join the source, injector and drain during play is done using well known techniques.

The metal line coupling the source region extends in the X direction, and the metal line coupling the injector and drain extends in the Y direction.

As shown in FIG. 1, ohmic contacts are formed in the source and conductor regions, while Schottky contacts are formed in the drain region.

Additionally, highly doped N+ region 22 separates the trapped charges in N-epitaxial region 40 from Schottky contact depletion region 51.

Region 22 prevents 5BD 80 from removing the stored charge in N- region 40.

This structure eliminates the need for external diodes for each memory cell when forming a two-dimensional memory array.

FIG. 2 shows a circuit of one memory cell, and FIG. 3 illustrates a memory array having four memory cells 11-22.

Each memory cell constitutes a single junction transistor.

When activated, the P+ injector region 72 and N+ source region 68 of FIG. 1 are held at ground potential, and the 5BD80
is forward biased with respect to the source, then N-region 4
Due to the high resistance of 0, a small current flows between the source and drain.

When P+ injector region 72 is forward biased with respect to source region 68, holes are injected from P+ region 72 into N− region 40.

Since the N+ reach-through region 22 is provided, no storage charge loss occurs.

Between the N region 68 and the N− region 40 and between the N+ region 70 and the N
The interface between the lJ region 400 contains two high concentrations -
There is a low concentration junction.

There is another high concentration low concentration junction between N+ region 20 and N− region 40.

The electric fields present at these junctions tend to block the migration of holes in the N+ regions.

Therefore, the injection tag from injector region 72 is stored in N-epitaxial region 40 .

If P+ injector region 72 is held at ground potential and drain region 80 with a low barrier SBD is biased with respect to source region 68 at ground potential, this low barrier SBD will not inject minority carriers.

However, due to the bias that exists between the SBD and the source region 68, the N
- A large current initially flows due to the holes stored in region 40.

When current flows through the device, the stored charge is removed, the resistance increases and the current drops to a low level.

By sensing the current at this time, it is possible to
It is possible to check the presence or absence of storage holes in the memory hole, and therefore, whether it is a binary 1 or a binary 0.

In operation of the array of FIG. 3, initially lines y1 and y2
is maintained at a low level ■1 as shown in FIG.

Line x1. x2 is initially kept at a high level V2.

Since the SBD receives a voltage of +yy2 on both sides thereof, the bias on the SBD is zero.

Therefore, no current flows and outputs 01 and 02 are both at high level V2.

This corresponds to the situation at point 1 in FIG. m of each memory cell! The resistance value is in a high state, ie, no stored charge, or in a low state, ie, a minority carrier charge is stored.

The operating cycle begins with a read operation as shown at point 2 in FIG.

When reading, it occurs simultaneously in the rows in the X direction, so it takes up one memory space.
A description will be given assuming that cells 21 and 22 are to be read.

When the line X2 is lowered to the low level v1, the device 21°22
Current flows through the devices 11 and 12, but since the line X1 is at the high level ■2, no current flows through the devices 11 and 12.

The magnitude of the current is determined by the charge stored in the device 21.22 from the previous cycle.

If no charge is stored in the device 21, the current will have a small value and the output 01 will only drop slightly as shown by the dashed line in FIG.

If there is no stored charge in the device 22, the output 02 will also drop only a little.

If a charge is stored in the device 21 or 22, a large current will flow and the output 01 or 02 will fall to a low level, as shown by the solid line in FIG.

When current flows through device 21 or 22, the stored charge is removed, the resistance increases and the current becomes a small value.

The output increases at level 1 shown by the broken line.

A sense amplifier (not shown) is connected to output lines 01 and 02 to distinguish between the outputs shown in dashed lines and the outputs shown in solid lines in FIG.

Since the read operation depletes the stored charge, a rewrite must be performed when the stored charge is sensed.

When writing charge to device 21, line y1 is raised to a high level 2, as at point 3 in FIG.

If a stored charge is detected as a result of sensing and it is desired to recover this same data or to write the charge independently of the previous data, line y1 is brought to a high level 2, but otherwise. It is kept at low level v1.

Device 22 can write simultaneously and independently by controlling line y2.

Quantity curve X1 of read and write operations for device 21.22
Cells 11 and 12 are not disturbed by these operations because they are kept at a high level ■2 and the SBDs of cells 11 and 12 are not forward biased.

Cells 11 and 12 are selected for reading and writing by bringing line X1 low and line X2 high.

As is clear from the above description, the N+ reach-through region 22 separates the N- epitaxial layer into two separate regions 40.
50 and serves to confine the storage charge within region 40.

This prevents loss of storage charge during the data retention period.

Without the N+ barrier region 22, minority carriers would diffuse into the depletion region of the SBD, causing loss.

The present invention also enables high density memory storage by eliminating individual external diodes for each cell through the use of SBD contacts.
You can shape the play.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of an integrated circuit of a memory cell according to the present invention, FIG. 2 is an equivalent circuit diagram of the memory cell of FIG. 1, and FIG. 3 is a circuit diagram of a 2×2 memory array. and the fourth
The figure is a timing diagram showing the operation of the memory array of FIG. 3. 10...Substrate, 20...N+ region 22...N-
isolation region, 40.50...N-epitaxial region,
68...N+ source region, 70...N10 region, 72
...P+injector area, 80...Schottky contact (drain pirate).

Claims (1)

[Claims] 1 a substrate, a first semiconductor layer of one conductivity type formed on the substrate, and a second semiconductor layer of the - conductivity type formed on the first semiconductor layer and having a lower doping concentration than the first semiconductor layer; means for separating the second semiconductor layer into first and second regions; an injector region of opposite conductivity type formed on a surface of the first region; and a means for separating the second semiconductor layer into first and second regions; A semiconductor memory comprising: a - conductivity type region having a higher doping concentration than a second semiconductor layer; a source region formed in the first region; and a Schottky contact providing a drain formed in the second region.