JPS5847057B2 - magnetic disk controller - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a magnetic disk control device, and more particularly to a magnetic disk control device whose data format is a fixed length type.

In a control device for a magnetic disk that has a fixed-length data format with a fixed data area, checking whether the various operations of the data error correction circuit are normal is to Also, there are considerable limitations because write operations can only be performed for each information block on the magnetic disk.

That is, in conventional magnetic disk control devices, arbitrary data can only be written to a magnetic disk in a predetermined data area, and arbitrary data cannot be written to an address area or an error correction code (FCC) area. I couldn't do it.

Therefore, it is very difficult to create arbitrary data errors on the magnetic disk and then check the operation of the data error correction circuit.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a magnetic disk control device that can easily check various operations of a data error correction circuit of a magnetic disk control device that employs a fixed-length data format.

The present invention is characterized in that it has a fixed length data format and is equipped with a circuit for correcting data errors based on the fixed length data format. is equipped with a means for writing data with any data length regardless of the data length, writes error data to a desired position on the magnetic disk using the means, reads the written position using a fixed length data format, and eliminates the error data. The reason is that the operation of the correction circuit is monitored.

The present invention will be described in detail below using the drawings.

FIG. 1 shows a block diagram of one embodiment of the invention.

In this figure, data recorded on a magnetic disk 1 is applied via a magnetic head 2 to a demodulation circuit 3 equipped with a VFO circuit, a PLO circuit, etc., and is demodulated. Converted to parallel.

The parallel converted data is transferred to a central processing unit (CPU) 7 via a read buffer 5 and a data line 6.

On the other hand, data transferred from the CPU via the data line 8 is applied to the write buffer 9 and then transferred to the shift register 4.
The demodulation circuit 3 and the magnetic head 2
is written onto the magnetic disk 1 via the .

The start and end timings of these data transfers are controlled based on signals sent from the transfer control circuit 10 to the CPU 7.

The read data output from the shift register 4 is also applied to two detectors 11 and 12.

The detector 11 detects the synchronization byte located at the head of the address area of the read data, and applies the detection signal of the synchronization byte to the address area counter 13 to start the counting operation of the counter 130.

A constant byte length corresponding to the address area is set in this counter 13, and is counted by a strobe.

During this counting, a signal is applied to the transfer control circuit 10,
It becomes possible to read the contents of the address area.

The detector 12 detects the synchronization byte located at the beginning of the data area of the read data, and the detection signal of the synchronization byte is applied to the set input terminal of the flip-flop 140.

The Q output of the flip-flop 14 is applied to the transfer control circuit 10 to enable transfer of read or write data, and is also applied to the data area counter 15.

An arbitrary byte length or a fixed byte length (256 bytes) is set in this data area counter 15 via a selection gate 16.

That is, when the selection gate 16 receives a variable operation command via the control line 16a, it supplies the variable data byte length sent via the tag bus line 16b to the data area counter 15, and normally outputs the variable data byte length via the control line 16d. When an operation command is received, a fixed data byte length (256 bytes) sent via the bus line 16c is supplied to the data area counter 15.

These byte lengths are set to the data area counter 15 by the sector pulse (
(during normal operation) or by tag gate pulse (during OT fluctuation operation).

The data area counter 15 counts the read or write byte length of the data area, and when this count becomes equal to the set number, that is, if the data area counter 15 is a down counter, its output becomes zero. If so, the decoder 18 detects this and resets the flip-flop 14.

As a result, the transfer control circuit 10 sends information to the CPU 7 to stop the data transfer.

Next, the data error correction circuit portion will be explained.

At the time of writing, when the address area counter 13 finishes counting, the ECC area counter 19 for each bit of ECC starts counting, and the FCC in the ECC register 20 is applied to the demodulation circuit 3 via the OR gate 21. The FCC is written to the next location of the address.

Similarly, after the data area counter 15 has finished counting, E
The CC counter 19 starts counting and the FCC is written to the next position of the data.

On the other hand, when reading from the magnetic disk 1, the demodulation circuit 3
The data from EC is input to the shift register 4 and the EC
It is also input to the C register 20 at the same time.

At the time when the ECC after the address or data area is read, the transfer control circuit 10 checks whether the contents of the ECC register 20 are all zeros, and thereby determines whether or not the data is checked.

Next, a procedure for actually checking the operation of the data error correction circuit using such a magnetic disk control device will be explained with reference to FIG.

First, a case will be described in which erroneous data is first created in the data area section and the operation of the error correction circuit is checked.

(1) Data area (DA) of record O on magnetic disk 1 recorded with a fixed byte length as shown in FIG.
) part and the error correction code (FCC) part of the DA part, the byte length (L2+C2) is set in the data area counter 15 using the method described above.

Next, based on the operation of the data area counter 15, the magnetic disk 10 performs a variable length read operation to store the contents of the DA part and its ECC part of record O in the memory in the CPU (see FIG. 2B).

(2) Modify the contents of the DA section stored in the memory with erroneous data within the correctable range of the error correction circuit.

(3) Change the data after this modification to the same byte length (L
2+C2) is set to data area counter 1.
A variable length write operation is performed based on the operation in step 5 to write to the DA section of record O and its ECC section.

(4) The normal operation of the error correction circuit is confirmed by performing a normal fixed-length read operation on the part of record O written in (3) and checking whether the error correction circuit has detected the data check. can.

Next, a case will be described in which erroneous data is created in the address area section and the operation of the error correction circuit is checked.

(1') Similarly to (1) above, the DA is stored on the CPU memory.
The section and its ECC section are stored by performing a variable length read operation.

Next, as shown in Fig. 2A and B, the above-mentioned DA section and its E
Following the contents of the CC part, the known byte length G3. G1. L
The contents of two gap sections having 1 and cl, an address area (AA) section, and an ECC section thereof are stored in memory.

(Two AA sections stored in memory or their ECC
Modify the contents of the section with incorrect data.

(3') As shown in FIG. 2 B and C, Lv=L2+C2+G3+G10L 1 +
Set the byte length of CI and use this data area counter 1.
A variable length write operation is performed based on the operation in step 5, and the contents in the memory are sequentially written from the DA section position of the magnetic disk 1.

(4') As shown in the second diagram, the error correction circuit performs a normal fixed length read operation for the address area part written with 00 and checks whether the error correction circuit has detected the data check. You can check the operation.

As explained above, although the device of the present invention has a magnetic disk control device that has a fixed-length data recording format, it has the ability to read and write variable-length data in which the byte length can be arbitrarily specified from the outside. This has the advantage that it is possible to modify data in any part of the magnetic disk, and that it is possible to easily check various functions of the data error correction circuit.

Therefore, by using this type of device, it becomes possible to diagnose the error correction circuit at the time of self-diagnosis of the CPU, which was not possible in the past, and the effects of the present invention are significant.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention.
FIG. 3 is an explanatory diagram of an example of the operation of the device shown in the figure. DESCRIPTION OF SYMBOLS 1... Magnetic disk, 2... Magnetic head, 3... Demodulation circuit, 4... Shift register, 5... Read shifter , 6, 8.1
6b, 16c...Bus line, 7...CP
U, 9...Write buffer, 10...
・Transfer control circuit, 11, 12...Detector, 13
・・・・・・Address area counter, 14・Song/flip-flop, 15・・Song data area counter, 16
...Selection gate, 17-...OR circuit, 1
8...Decoder, 19...ECC area counter.

Claims (1)

[Claims] 1. In a magnetic disk control device that has a fixed length data format and is equipped with a circuit that corrects data errors based on the fixed length data format, data can be written with any data length regardless of the fixed length data format. Error data is written to a desired position on the magnetic disk using the means, and the writing position is read out using a fixed length data format to monitor the operation of the error correction circuit. A magnetic disk control device characterized by: