JPS5847192B2 - Electronically controlled pattern sewing machine - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a control device for a sewing machine equipped with a pattern forming device that changes the relative position of a cloth and a needle to form a pattern using stitches, and particularly relates to a control device for a sewing machine equipped with a pattern forming device that changes the relative position of a cloth and a needle to form a pattern using stitches. The present invention relates to an electronic control device that stores signals related to stitch control in a computer and forms a sewing pattern by electronic control.

This type of sewing machine, which is currently in widespread use, uses a mechanical storage device, such as a pattern cam, to sew patterns, but as the storage capacity increases, the mechanism becomes more complex and there is a shortage of space to accommodate it. However, a method of controlling the pattern forming device using an electronic storage device has been proposed, and this method can cope with the increase in storage capacity. However, in that case, it is desirable to have something that can effectively utilize the stored contents to fully respond to the diversification of patterns.

The present invention was developed in response to such a demand, and its purpose is to store signals related to seam control in an electronic storage device, and to create a control system that enables sewing patterns to be formed by electronic control. The present invention aims to provide a control method which, when applied, leads to effective utilization of the storage capacity of an electronic storage device, coping with the diversification of patterns, etc.

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic diagram of a sewing machine according to the present invention, and 1 is a sewing machine frame;
2 is an upper shaft, 3 is a lower shaft, 4 is a needle bar, 5 is a cloth feed dog, and 6 is a thread ring capture device. When the upper shaft 2 is rotated by an electric motor, etc., the needle bar 4 is moved through a crank mechanism, etc. The lower shaft 3 is rotated via the timing belt γ, and the thread ring catching device 6 is further moved.

Reference numeral 10 denotes a pattern forming device, and the amplitude adjustment output from this device gives a swing motion to the amplitude adjustment arm 9 via the amplitude adjustment output 8, and is applied to the needle bar 4 via the amplitude rod 11. Give a movement during needle vibration.

Further, the pattern forming device 10 applies a cloth feed adjustment output to the cloth feed adjustment output arm 12 , gives a swinging motion to the feed adjustment arm 13 , and gives a cloth feed movement to the feed dog 5 via the feed adjustment rod 14 .

Furthermore, the pattern forming device 10 uses a stitch control signal outputted from a control circuit shown in FIG. 2 (or FIG. 4) to be described later to a driving solenoid s.

.

Reference numeral 20 indicates a housing portion for the control circuit.

A phototransistor 15 receives light from a light emitting diode 18 through a notch 17 in a shield plate 16 fixed to the upper shaft 2, and outputs a signal synchronized with the rotation of the sewing machine to a control circuit.

SW0 to SW6 provided on the front surface of the sewing machine are pattern selection switches, and by operating the switches, the operator can select a desired sewing pattern.

The pattern forming device 10 includes an adding mechanism (not shown) and a solenoid S for driving the adding mechanism.

+ Sl t 82 constitutes a set of an adding device, another adding mechanism (not shown), and a solenoid S for driving the same.

+ S 1 w S 2 constitutes a set of adding devices for needle swing middle leg joints and cloth feed adjustment, and output arms 8 and 12 of these adding devices provide a swing width adjustment arm 9 and a feed adjustment arm 13.
Give momentum to each.

These adding devices are each solenoid S. , S1j S2 and S'0 + S'1, S'2 are operated individually to give a displacement amount of relative ratio 1:2:4 to each output arm 8.12, and by combining these, the displacement is The configuration is such that the amounts are added and each can give a displacement amount of 0 to 6.

Next, to explain the configuration of a control circuit that provides stitch control signals to the pattern forming device 10, FIG. However, the cloth feeding control may be controlled using a similar configuration or by sharing a portion thereof.

In Fig. 2, 5w1-5w5 are normally open pattern selection switches, each one end of which is grounded, and each other end connected to a NAND circuit N.
It is connected to the trigger terminal Cp of the monostable circuit MM1 via AI, and the operating state of the switch is set to a logic value of 11.
NAND circuit NAI to encode from 000 to 100 on the condition that it does not contain 1.

NA2. It is connected to the input side of the latch circuit L1 via NA3.

Note that Vcc is a DC power supply for control, and R1 is a normally used limiting resistor.

The positive output terminal Q of the monostable circuit MMI is connected to the trigger terminal cp of the latch circuit L1, and when any of the switches SW1 to SW5 is operated, the output terminal d3. d2. The encoded signal is outputted at d1.

C is a counter configured in a master-slave manner, and its reset terminal R is connected to the negative output terminal station of the monostable circuit MMI, and each output terminal A has 5 bits.

-A4 is each input terminal A'o-' of the electronic storage dose ROM
-A', respectively, and each time a pulse force φ1, which will be described later, is received at the input terminal Cp, it is counted and advances the address of the storage device ROM, and has a predetermined total count value. The total number is a number that includes the total number of memory locations from which the memory device ROM reads out each stitch control signal for a plurality of patterns one by one for each sewing day, and the number is The first thing to be mentioned later
This is indicated by the total number of addresses in the table, which is 25 in this embodiment.

In other words, in this embodiment, one person can use A4.
A3. A2. A1. When Ao reaches 25 in decimal notation, or code 11001, it returns to 0, or ooooo, and each stitch has a number equivalent to the total number of stitches across multiple patterns that the sewing machine can sew in this case. Control signals are arranged and stored in these 25 storage locations.

Each output D1, D2, of the storage device ROM. D3 is paired with the output d1 s d2 +d3 of the latch circuit L1, respectively, to exclusive OR circuits EXORI and EXOR2.
, EXOR3, each output of the exclusive OR circuit serves as each input of the OR circuit ORI, the output of the OR circuit serves as one input of the AND circuit AND1, and the other input of the AND circuit serves as a memory. Each output D1 of the device ROM. D2. D
3 as an input, receives the output of the OR circuit OR2, and performs the AND
The output of the circuit AND1 is a D-type flip-flop circuit F/F.
connected to the data terminal of the

Although not shown, the output Q of the flip-flop circuit is reset to O when the control power supply Vcc is turned on, and the output terminal Q is connected to an astable circuit AM.
The pulse output terminal φ1 of the astable circuit AM is connected to the input terminal IN of the delay circuit TD and to the input terminal Cp of the counter C.

The output terminal φ2 of the delay circuit TD and the positive output terminal Q of the monostable circuit MM1 are connected to the trigger terminal Cp of the flip-flop circuit F/F via a NOR circuit N0RI. .

Among the outputs of the storage device ROM, Dl, D2 . D3 serves as each input of the AND circuit AND2, and the output of the AND circuit is used as the upper bit of the 2-bit input of the master-slave type 3-bit full adder FA, and is outputted.

is the lower bit.

and output B of adder FA.

A code consisting of f B and l B2 is fed back as the augend of the adder and forms the input.

The adder has a reset terminal R connected to the negative output terminal Q of the monostable circuit MMI, and a trigger terminal cp connected to N0.
The output φ3 of R1 is received, and each time the pulse signal φ3 is received, the 3-bit output code of the adder is stored in the storage device R.
It forms the main element of the output counter that adds the 2-bit addition number from OM and outputs a 3-bit code, and the counting by the addition progresses according to the count of the counter C, as described later. and one cycle of counting by the addition consists of a number obtained by dividing the total count value of the counter C, and by repeating the cycle of counting, the number of progresses over the total number of each memory location in the storage device ROM. are counted sequentially.

In this embodiment, the adder is O~ in decimal notation.
6 outputs are possible, and 111 out of 3 bit outputs are possible.
is prohibited.

The output of the adder serves as an input to the latch circuit L2, and each output O8°01.02 of the latch circuit is connected to each solenoid So, Sl, B2 of the pattern forming device 10, respectively.

P and S are position detectors whose main element is the phototransistor 15, and a monostable circuit M connected to the output terminal OUT of the needle bar at a predetermined position every time the upper shaft 2 of the sewing machine rotates once.
A synchronization signal with the rotation of the sewing machine is sent to the trigger terminal cp of M2, and at that time, the preset terminal P of the flip-flop circuit F/F connected to the negative output terminal Q of the monostable circuit is sent.
A signal is applied to the trigger terminal Cp of the latch circuit L2 and the flip-flop circuit is preset at the falling edge of the signal, and the latch circuit L2 latches the output of the adder FA and outputs it to the pattern forming apparatus 10. ing.

The storage device ROM receives inputs A'41 A'31 A'21 A'1 in order to form a plurality of patterns as shown in FIG.
The address code consisting of 1A'o is O in decimal notation.
25, each signal to be output to the terminals D3 + D2 + Dl + D□ shown in Table 1 as an example is stored as will be described later.

In the above configuration, referring to FIG. 2, the control power supply Vc
When c is input, the output Q of the flip-flop circuit F/F becomes the logical value O, and the pulse output φ1 of the astable circuit AM
There isn't.

Next, when the pattern selection switch SW3 is operated to select an arbitrary pattern, for example, pattern 3 in Fig. 3, the latch circuit L
1 output d3. d2. d1 is latched to logic value 010.

At this time, counter C and adder FA are reset.

Counter C becomes the first address O in Table 1,
Output code of storage device ROM D3°D2. Dl and Do become oooo depending on the correspondence in the table.

Therefore, the output of OR circuit OR2 is set to O, and latch circuit L1
The output d1. d2. Regardless of the value of d3, the data terminal of the flip-flop circuit F/F is set to O and its output Q is not inverted.

Therefore, there is no output φ1 of the astable circuits A and M, and the counter C does not operate.

Adder FA is connected to monostable circuit M after operating switch SW3.
MI becomes inoperable and the reset is released), but since the addition input AND2 and Do are OO, the output B2. B1.
Bo is 000 without being added with a reset value due to the output φ3 of the NOR circuit N0RI when the positive output Q of the monostable circuit MM1 falls.

Next, when the sewing machine rotates and the position detectors P and S reach predetermined positions, the monostable circuit MM2 is tripped and its output Q triggers the latch circuit L2, and the output B2.
B1. Connect Bo to terminal 02. Ol and Oo are latched and the first stitch signal 000 of pattern 3 is output to the pattern forming device 10.

At the same time, the output signal Q of the monostable circuit MM2 presets the flip-flop circuit F/F, releases the reset of the astable circuit AM, and counts up the continuous pulse output φ1 of a period significantly faster than the sewing machine rotation period or the counter C.

Since the counter is of a mask slave type, the counted contents are sent to the terminal A every time the pulse φ1 falls.

- Output from A4. Then, by the first count, the decimal output becomes 1, that is, the output D3. of the storage device ROM corresponds to address 1 in Table 1. D2. D1. Do is 11
It becomes 10.

This output 1110 is the addition input AND2. D
.

Output B2. as code 10, that is, decimal number 2. BlBo
are the signals 000 to 010 of the first stitch.

At this time, the output ct3 of the latch circuit L1. ct2+ct.
010 and output D3. D2. It is compared with 111 of D1, the data terminal of the flip-flop circuit F/F is set to 1, its output Q is maintained at 1, and the counter C advances the count.

Then, when the output of the storage device ROM becomes 0100 corresponding to address 2 by the next count, the latch circuit L1
It is compared with the output 010 of the OR circuit and becomes OR1 or O.
Therefore, the data terminal of the flip-flop circuit F/F is set to 0.
At the falling edge of the output φ2 of the delay circuit TD, the output Q
is reversed, and the pulse φ is stopped.

The output 0100 of the storage device ROM is set to the addition input of the adder FA as OO, and its output 010 is not changed.

Next, when the sewing machine continues to rotate and the position detectors P and S reach predetermined positions, the latch circuit L2 is triggered and outputs the second stitch signal 010 of pattern 3 to the pattern forming device 10.

At the same time, the flip-flop circuit F/F is preset,
Counter C counts up.

Similarly, the output D3 of the storage device ROM. D2. D1 is 0
Counter C stops counting up each time the value reaches 00 or 010.

That is, the third stitch signal is 100 corresponding to address 4 according to Table 1, and the fourth stitch signal is 11 (corresponding to address 6).
The h fifth stitch corresponds to address 10 and becomes 1001, and the sixth stitch corresponds to address 15 and becomes 010, and these are output to the pattern forming device 10 each time the sewing machine rotates.

The code structure according to Table 1 corresponds to the final count of 25 in the counting capacity of counter C and the outputs of adder FA B21B1. Bo is OOO.

That is, adder FA outputs B25B1 . Reset Bo to 000.

Therefore, in this operation example, after the sixth stitch, the counter C outputs address 25, then outputs address O on the next page, and the count-up stops for the first stitch, and the output of the storage device ROM at this time is Output B2+B1. Bo's OOO is not added.

Thereafter, pattern 3 is repeated in the same way.

Note that FIG. 3 shows an example of a pattern in which the cloth feed is constant.

Next, to explain the formation of the storage contents of the storage device ROM shown in Table 1, first, each pattern needle width coordinate O shown in FIG.
The output of adder FA for .about.6 B2. B1. Taking the coordinate code OOO~110 consisting of Bo as an example, as shown in Table 2, one cycle is defined as sequentially increasing from 000 until it reaches 110, and the cycles are repeatedly listed.

Next, send the listed order and write the pattern numbers in FIG. 3 in the order of the stitch numbers of each pattern.

For example, in Table 2, code 001 in the second row matches the coordinates of stitch number 3 of pattern 4, but since pattern 4 does not have stitch number 2 placed above it (first row), it is left blank.

These blank codes are deleted using -.

And the coordinate codes 000 and 11 commonly included in each pattern
The pattern number will be written redundantly corresponding to only 0.

Continue this process until each pattern is completed.

Therefore, in Table 2, pattern number 1 is completed in stages 1 to 7, so there is no duplicate entry corresponding to coordinate code 000 in stage 8.

Next, each output D3 of the storage device ROM. D2. D1. Do
In determining , first let the outputs of the first stage and seventh stage described above be oooo.

This means that the upper 3 bits 000 are OR circuit O in common to each pattern.
This is to stop the counter C from counting by setting the output of the flip-flop circuit F/F to O via R2.This 3-bit OOO and the least significant bit O are input to the addition input AND2. Do is set as OO.

Therefore, the first row is created corresponding to address 0 in Table 1.

Next, since there is no corresponding pattern in the second row of Table 2, in order to move to the third row, that is, to change the coordinate code from OOO to OlO, the output of the storage device ROM is changed so that the upper 3 bits do not include the pattern selection signal. However, if it is 1110, the adder FA
Addition input AND2, Do is 10, i.e. 1O base addition number 2
shall be.

Therefore, the coordinate output B2 y B 1 *BO becomes 010 without outputting 001.

Therefore, the second stage corresponding to address 1 in the first table is created.

Next, without advancing the coordinate code, in order to stop the counter C at code 010 on the condition that pattern 3 is selected, the output of the storage device ROM includes 010 in the upper 3 bits (hereinafter referred to as the pattern selection code). does not include 111 in the upper 3 bits, so the AND circuit AND2 becomes O and the upper addition bit of adder FA is O), and the least significant bit is O, that is, 0100 where the addition number of adder FA is O. shall be.

Therefore, the third stage corresponding to address 2 in Table 1 is created.

Next, on the condition that pattern 2 is selected, stop the counter C at the code 001 and change the coordinate code to 010.
To advance from 011 to 011, that is, add 1 in decimal, the output of the storage ROM becomes 0011, and the fourth value in Table 2
A rung is created.

The 5th to 9th rows are created in the same way, and the 10th row has two blank rows in Table 2, so the output of the storage device ROM does not include the pattern selection code in order to convert the addition input into ternary decimal numbers. 1111.

Similarly, each row of Table 2 is created, and the selection code 100 of pattern 5 corresponds to address 25. Therefore, when pattern 5 is selected, counter C stops at address output 25, but other When the pattern is , the process moves to address O.

The output 0000 of the storage device ROM is the output B2. at address 25. B1. 000 of Bo is not added.

This means resetting the output B2 s Bl + BO at address 25.

As described above, the 25 addresses in Table 1 are sequentially advanced by the counter C, and all the storage locations of the stitch control signals of each pattern are located within these 25 addresses.

Then, in Table 1 or Table 2, adder FA
Symbol D3. D2. The positions of each address corresponding to the code pattern number consisting of D1, that is, the address of data used for each stitch control, are indicated by symbol B2. B1
．． Using a code consisting of Bo, one cycle is defined as the code increasing sequentially from 000 to 110 as the address progresses, and counting is performed by repeating this cycle.

In addition, in Table 1, address 15.16 is B3 + D2
．． The codes consisting of D1 are 010 and 011, respectively, which correspond to 1 and pattern numbers 3 and 4, respectively, and B2.
B1. The codes consisting of Bo are both 010 and do not depend on the progression of addresses, but this happens to be at address 1.
This occurred exceptionally because the coordinates of the stitches to be placed at either No. 5 or No. 16 coincided with each other.

Next, to explain that one of the features of the present invention is that it is possible to create a pattern by combining the data of a plurality of these patterns, the data of patterns 3 and 5 in FIG. In order to create the same, a part of the control circuit shown in FIG. 2 is changed as shown in FIG. 4.

This is the output D3 as the address advances in Table 1.
．． D2. D1 is 000 common to each pattern and 0 corresponding to pattern 3 10. This is to stop the counter C when it reaches 100, which corresponds to pattern 5.
A combined pattern is created as shown in the figure.

To explain FIG. 4 in detail, the switch SW6 is a pattern selection switch for selecting the combined pattern shown in FIG. 7, and when this switch is operated, the output d3 of the launch circuit L1. d2. Code 101 is latched in d1.

Inverter IN1゜■N2 is the latch circuit L1 of the OR circuit OR3, which is the input of the AND circuit AND1.
If the input from is 000 when the code is 101,
Output D1 of the storage device ROM only when switch SW6 is operated
This is to make it valid as an input to the OR circuit OR3.

Since the output D1 of the storage device ROM is O only for the common pattern and patterns 3 and 5, the switch SW
6 is operated, the output D1 in Table 1 is O, and each coordinate data B2. B1. As Bo advances in address, the pattern shown in FIG. 5 is formed.

As described above, in the present invention, the storage device ROM does not store individual stitch signals, but outputs a signal for selectively stopping a counter input receiving a constant periodic signal that addresses the storage device, for example. The adder output is made in relation to the output of the storage device at the time of stopping, and is made to correspond to the coordinates specified for each selected sewing pattern and the stitch number. In this case, the same code in the storage device ROM can correspond to multiple stitch coordinates, and as shown in this embodiment, the adder output can be reset to OOO at the final count of the counter without using a specific reset device. However, the reset signal can also be used as a stitch code for a specific pattern if necessary, making it possible to form many patterns with a small amount of memory content in the storage device ROM, and moreover, it is possible to form multiple patterns as shown in Fig. 5. The circuit configuration for creating a pattern by combining the data of be.

[Brief explanation of the drawing]

The drawings show embodiments of the present invention; FIG. 1 is a schematic diagram of a sewing machine according to the present invention, FIG. 2 is a control circuit diagram according to the present invention, FIG. 3 is an example of a sewing pattern, and FIG. 4 is an example of creating a combination pattern. A partially modified view of FIG. 2 and FIG. 5 are examples of combination patterns. In the figure, 10 is a pattern forming device, switches SW1 to SW6 are the main elements of the pattern selection device, ROM is an electronic storage device, monostable circuits A and M are oscillators, C is an address counter,
Flip-flop [2m F/F is the main element of the stop device, adder FA is the main element of the output counter, detectors P, S are the main elements of the synchronization signal generator.

Claims (1)

[Claims] 1 In a sewing machine equipped with a pattern forming device that forms stitches by changing the relative position of the fabric and needle using an electromechanical transducer, the machine operator operates the sewing machine to select a desired pattern from among multiple patterns. a pattern selection device that generates a code signal specific to each of the plurality of patterns; a storage device that stores a code specific to each of the plurality of patterns; and an address code indicating the order of the storage location of each of the plurality of patterns; an electronic storage device that corresponds in relation to codes specifying the coordinates of each stitch, and for each individual pattern, the storage order of the unique codes is in accordance with the progression order of stitch signals indicating the stitch order; a synchronous signal generator that generates a signal synchronized with the up and down movement of the needle of the sewing machine; a oscillator that generates a free-running signal; and a synchronous signal generator that starts counting the signals of the oscillator based on the signal of the synchronous signal generator and stores the signal. An address counter that sequentially corresponds to the storage locations of each data of a plurality of patterns in order to read data from the device, and has a predetermined total count value, and the total count value includes the total number of the storage locations. The number of progresses of the storage location is sequentially counted over the total number of storage locations using the output signal from the storage location of the storage device based on the designation of the address counter, and one cycle of the counting corresponds to the number of storage locations in the storage device. an output counter which counts over the total number of memory locations by repeating the counting cycle and provides the result to the pattern forming device; Each time the address counter matches a code signal specific to the selected pattern, counting of the address counter is stopped, and the value of the output counter counted based on the output signal is sent to the pattern forming device as the stitch of the selected pattern. An electronically controlled pattern sewing machine is provided with a stop device that makes the sewing machine effective.