JPS5847742B2 - Memory control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a storage control method, and specifically to an improvement in a memory system control method that is effective for information processing systems that require conversion from logical addresses to physical addresses.

It is known to add segments as a means of expanding storage space in memory systems implemented as main memory.

In other words, there are two types of addresses: physical addresses and logical addresses. A physical address is a unique address possessed by each memory module (for example, in units of 16 Kbytes) installed as main memory, and can be specified from 0 to 512 Kbytes, for example. , is used to specify one address in the memory system in terms of hardware.

Also, a logical address is a logical address when a program
In this embodiment, up to 64K bytes can be specified within one segment.

Therefore, since a logical address does not directly specify a physical address, the logical address is converted into a physical address and access to the main memory is performed.

On the other hand, recently, 16K dynamic MOS is used as a memory element.
4K-16 pin dynamic MOS has been put into practical use and is increasingly being applied to minicomputers (and equivalent models) and mainframes, making it possible to greatly improve the pit density of boards compared to current designs using 4K RAM.

To briefly explain this memory element using the timing chart of the READ/WRITE cycle in Figure 1, it is necessary to decode one of the 16384 cells.
The four address bits are multiplexed to seven address inputs and latched into on-chip address latches by two external negative TTL-level clocks.

First clock, row address strobe (RAS)
latches 7 column address bits into the chip.

Second clock, line address strobe (CAS)
subsequently latches the 7 row address bits into the chip.

Each RAS and CAS signal triggers a series of operations controlled by a different delayed internal clock.

The two clocks are logically linked to allow address multiplexing to occur outside of the critical timing sequence during read data accesses.

In-chip operation with CAS clocks is created from the RAS clock chain.

This so-called gated CAS feature satisfies the column address hold time (tRAH), and as soon as the address input changes from a column address to a row address, the external You can insert the CAS clock from here.

CAS can be inserted at any time after tRAH, and RA
The worst-case access time (tRA
S).

By internally gating CAS in this way, tRC
Two timing standards are created called D (minimum) and tRCD (maximum).

If CAS is inserted later than tRcD (maximum), errors may occur in data reading and writing, but if this is done, the access time will be determined by the access time from CAS and not from RAS.

In other words, the access time from RAS is t'RCD (maximum)
Soak for as long as CAS exceeds.

Data written to a selected cell is latched into an on-chip register by ANDing WRITE and CAS when RAS is active.

Either WRITE or CAS is connected to the strobe of the data-in (Din) register.

Therefore, there are several options for write cycle timing.

In a write cycle, prior to CAS, when the write input goes low, Din is stroped by CAS,
Data setup and hold times are referenced to CAS.

If the input data is not yet ready when CAS enters, or if a read/write cycle is preferable,
WRITE can be delayed until there is a negative edge of CAS.

In this ``delayed write cycle,'' data input setup and hold times are
It is referenced to the negative edge of WRITE.

(This is shown in the timing diagram, where for read-write and page-mode write cycles, Din also WRITEs the ``Early Write''
cycle” is referenced to CAS) CA
Data is retrieved from memory by keeping WRITE high while S is low.

The data read from the selected cell in the memory is to be output by a specified access time.

The characteristics of an information processing system that requires 16K dynamic RAM and logical address to physical address conversion are listed below (IX2). When adopted in a system, the following drawbacks occur: (3).

(1) 16K dynamic MOS, 4K-16 pin dynamic MOS memory elements require the address to be given to the memory chip twice, so half of the bits of the address information passed to the memory chip are more sensitive than the other half of the bits. may also be confirmed after a time delay.

(2) Conversion from a logical address to a physical address takes more time than the conventional system because of the indexing of the conversion table.

However, only a portion of the address information is affected by the conversion.

(3) Since the reception of row addresses and column addresses and the address conversion using the address conversion table were performed sequentially, access time became long, which in turn led to a decrease in the performance of the entire system.

The present invention has been made in view of the above-mentioned drawbacks, and an address circuit is configured such that the bit affected by the address conversion is always a column address (the address received for the second time) when viewed from the memory chip, To provide a storage control method that speeds up a memory system and shortens access time by giving a low address to a memory chip and starting a memory cycle long after an address conversion circuit completes its operation. With the goal.

Hereinafter, the present invention will be explained in detail using FIG. 2 and subsequent figures.

FIG. 2 shows an embodiment of an information processing system for embodying the storage control method of the present invention.

In the figure, reference numeral 1 denotes a CPU which is the central part of the system and controls the entire system as well as address translation in areas particularly relevant to the present invention. 2 is a memory subsystem consisting of a 16K dynamic RAM chip and its control section.

Further, in the CPUI, 3 is a 3-pit segment register SGR that specifies one of the eight segments.
4 is a logical address register LA that stores logical addresses.
R, and consists of a logical block LB consisting of the upper 3 bits of the logical address and the remaining 13 bits of displacement.

Further, 5 is an address conversion table for converting a logical address into a physical address, which determines for each system how each segment is configured with i physical blocks, that is, determines the physical blocks etc. that are commonly used in each segment. Since this segment table is stored, address conversion is performed using this address conversion table CT5 and the segment register SGR3.

On the other hand, in the memory subsystem 2, 6 is set to the output of the address conversion table CT5, and a 7-bit column address register ABC, 7 is a 13-bit column address register to which the displacement part of the logical address LAR4 is set. Row address register ARL, 8
selects one of the rows and columns,
A selector 9 outputs address information to the address line of each memory chip, and is a control circuit that operates by overlapping the reception of the row address of the memory subsystem 2 and the address conversion by the address conversion table CT5. be.

In other words, the bit affected by address conversion is always the column address (the address received the second time) when viewed from the memory chip, and the memory cycle is started by giving a row address to the memory chip as soon as the address conversion circuit completes its operation. It is operated so that it starts.

The control circuit 9 also receives bits 11 to 15 of the ARR 7 and performs well-known operations such as generating a chip select signal and specifying an addressed byte among a plurality of bytes read and written simultaneously.

The operation of the embodiment shown in FIG. 2 will be explained in detail below using the operation timing chart shown in FIG.

In Figure 3, from top to bottom, the basic clock, segment number, intra-segment address, address conversion table output, memory start signal, RAS signal in the memory subsystem, CAS signal, row address stroke signal, and row address register. Output, column address strobe signal, column address register output, and memory chip address information are shown.

In the present invention, since a logical address does not directly designate a physical address, the logical address is converted into a physical address and the main memory is accessed.

This conversion is performed in units of 8K byte blocks.

In other words, the lower 13 bits of the logical address (8K byte address) are directly the lower 13 bits of the physical address,
Directly assigned as a row address.

The upper 3 bits (logical block) of the logical address are then converted into the upper 6 bits (physical block) of the physical address.

This is done by segment register SDR3 and address translation table CT5.

That is, the 3-bit segment register SGR3 specifies one of the eight segments.

Each segment is a maximum of 64K bytes in size, each with 8
It is composed of two physical blocks.

The address translation table CT5 stores this physical block number.

First, a segment is selected by the segment register SGR3, a physical block is indexed by a logical block, and a physical address is determined.

The system determines what kind of physical blocks each segment should be organized into, that is, the physical blocks commonly used in each segment, and this segment structure table is stored in the address translation table CT5. be.

The address information passed through this address conversion table CT5 is assigned as a column address, and latched into the column address register by the strobe signal $ARC.
In addition, the row address directly allocated as a memory address is latched into the row address register ARR7 by the strobe signal $ARR.

In terms of timing, reception of a row address directly designated as a memory address and address conversion table CT5
This overlaps the address translation and address conversion.

However, in the above embodiment, the row address register ARR
7. Two timings were required to strobe the column address register ARC6, but in order to unify this timing into one, it is better to use a latch instead of the register.

That is, the two registers ARC6 and ARR7 in FIG. 2 are combined into one latch register AIR, and the control gate signal of the latch register AR is $AR.

A timing chart when this latch register AR is used is shown in FIG.

As explained above, according to the present invention, 16K dynamic M
Allocate 6 bits of the memory address that will be converted by the conversion table to the column address of the OS memory, create the address between the address conversion table and the memory chip using a register or two registers with different strobe timings, and convert the row address to the column address of the OS memory. Memory access time can be shortened by overlapping the reception and address translation operations.

[Brief explanation of drawings]

Figure 1 shows the READ/
WRITE cycle timing chart, FIG. 2 is an embodiment of the storage control method of the present invention, FIG. 3 is an operation timing chart of FIG. 2, and FIG. 4 is an operation timing chart of another embodiment. It is. 1...CPU, 2...Memory subsystem, 3...Segment register, 4...
...Logical address register, 5...Address conversion table, 6...Column address register,
7...Low address register, 8...
Selector, 9... Control circuit.

Claims (1)

[Scope of Claims] 1. A storage device configured with a storage element that receives address information at two timings, a first address transfer period and a subsequent second address transfer period, and a logical address used in a program that accesses the storage device. and an address conversion circuit for converting the address information into a physical address, the circuit for providing the address information to the storage element converts the address information obtained from the address conversion circuit into the second address period. 1. A storage control method, wherein the storage device is configured to transfer only the address conversion circuit, and the storage device starts operating before the output signal of the address conversion circuit is determined. 2 A first address register that holds address information for a part of the physical address and an address register that holds address information for the remaining part of the physical address, and the data input of the circuit that provides the address information is 1, connected to the second address register output;
2. The address register according to claim 1, wherein the address register is also strobed before the second address register, and the output of the address conversion circuit is supplied to the second address register. Memory control method. 3 A storage device configured with a storage element that receives address information at two timings, a first address transfer period and a subsequent second address transfer period, and converts a logical address used in a program into a physical address for accessing the storage device. and an address translation circuit for the purpose of assigning the address information that has passed through the address translation circuit as an address to be received during the second address transfer period, and combining the output of the address translation circuit with the logic A storage control method comprising means for latching address information that is directly used as a physical address among address information, and in which acceptance of an address by the latch and address conversion operation by the address conversion circuit are overlapped.