JPS5847783B2 - Memory access processing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a memory access processing method, . In particular, a floating memory device is equipped with a storage device having a plurality of storage units that can be accessed independently, and the correspondence between part of bit information in given address information and the storage unit is variable.
The present invention relates to a memory access processing method in which the above-mentioned association is performed by a floating memory address conversion memory in a memory addressing method, and the association is rewritable.

Conventionally, in a memory access processing method that employs a so-called floating memory address method, the correspondence between the above storage unit and part of bit information in given address information is shown in FIG. 1 as described later. Provision is made in a floating address register.

However, when using the floating address register, as the number of storage units increases, the amount of hardware increases, and if the operator wants to freely handle changes in the capacity of the storage unit, the operator cannot change the register. Content management becomes extremely complicated.

The present invention aims to solve the above-mentioned problems, and the memory access processing method of the present invention includes a storage device having a plurality of storage units that can be accessed independently. Alternatively, in a memory access processing method in which the storage unit is selected based on a plurality of bit information and the correspondence between the bit information and the storage unit is made variable, there is a one-to-one correspondence with the bit information in the address information. A floating memory/address conversion memory is provided, which has a designated address position and rewritably stores designation information specifying one of the pupil units in the address position, and the floating memory/address conversion memory is read from the floating memory/address conversion memory. In addition to selecting the storage unit based on the content, some bits of the bit information in the address information are used as address information for selecting the address position corresponding to the number of address positions in the storage unit. In addition, in the floating memory/address conversion memory, the same designation information that designates the pupil unit is stored in a plurality of address positions that differ only in some of the bits of the bit information. The feature is that it can be stored.

This will be explained below with reference to the drawings. FIG. 1 is an example of a conventional method, FIG. 2 is an example of the configuration of an embodiment representing the overall concept of the present invention, and FIG. 3 is an explanation illustrating a mode of dealing with an increase or decrease in the capacity of a storage unit when the present invention is used. Show the diagram.

In FIG. 1, 1 is an address register, 20 through 2-n are storage modules, and 3-ro through 3-n are respectively memory modules.
n are floating address registers, 4-
0 to 4-n each represent a comparison circuit.

In the floating address register 3, a floating address is set, for example, by an operator from the console.

For example, set "01" in #0 register 3-0,
If "00" is set in 1 register 3-1,
Address information given by the central processing unit and/or channel to access the memory device.
For example, the upper 2 bits of (set in register 1) are “
00'', the comparator circuit 4-1 issues a coincidence output and issues an enable signal to the storage module 2-1.

Meanwhile, the remaining bit information of address register 1 is supplied to each storage module 2-ro to 2-n.

For this purpose, a predetermined intra-module address within the storage module 2-1 is accessed.

For example, if the operator sets "00" in the floating address register 3-n and erases the contents of the register 31 due to a failure in the storage module 2-1, the same address information as above When is set in the address register 1, an enable signal is supplied to the storage module 2-n, which has been kept as a reserve until then.

The floating memory addressing method is structured as described above, but when the number of storage modules, and furthermore, the number of storage banks when the module is divided into banks that can be accessed independently, becomes large. Accordingly, the number of floating address registers 3 increases, and the number of comparison circuits 4 increases accordingly.

Furthermore, the floating address register 3 has a fixed bit width.

Therefore, when increasing the capacity of each storage unit, some bits of the floating address register become unnecessary for selecting the storage unit, but management and modification of the comparator circuit 4 are required for this purpose. Become.

The present invention solves the above-mentioned problems, and FIG. 2 shows the structure of an embodiment representing the overall concept of the present invention.

Codes in the figure: 1. 2-0. 2-1. 2-n corresponds to FIG. 1, 5-00..., 5-1 0,...
. . represents a memory bank in which one storage module is divided into a plurality of banks; 6 represents a floating memory/address conversion memory produced according to the present invention; and 7 represents a decoder.

At each address of the floating memory/address conversion memory 6, for example, a storage module instruction bit (MSU A), a storage bank instruction bit (BANKA), and a mounting/non-implementing instruction flag (L/UL) are stored as a set. Ru.

For example, $IM is placed at address ``OOOOJ'' in memory 6.
The information specifying #3 bank 5-13 in SU is
Assuming that information specifying #0 bank 5-10 in lIMSU is stored at address 0011, for example, if the upper bit of the address information set in address register 1 has "OOOl". Then, address “OOO1” of memory 6 is accessed, and decoder 7
An enable signal is supplied to the #0 bank 5-10 in the lIMSU by the output of the IIMSU.

Since the remaining bits in the contents of address register 1 are supplied to each memory bank in parallel, a predetermined intra-bank address in memory banks 5-10 is accessed.

In the case shown in the figure, an installed/uninstalled flag (L/UL) is added to the contents of each address in the memory 6, and if the memory bank indicated by the contents of the address register 1 is not installed, the decoder 7 The output of is considered invalid.

This prevents unimplemented storage units from being accessed by mistake.

In the case of the present invention, by rewriting the information stored in each address of the memory 6, even if the upper bits in the contents of the address register 1 have the same 1-0001J, for example, #n M S U This means that the enable signal can be supplied to #3 bank 5-n3.

In the case of the present invention, by using the floating memory address conversion memory 6, the hardware configuration of the part that sets the floating address is extremely compact and simplified.

Furthermore, changes such as increasing the capacity (number of addresses in the bank) of the storage bank 5 shown in FIG. 2 can be easily coped with.

FIG. 3 illustrates one aspect thereof.

Reference numbers 1, 6, and 7 in the figure correspond to those in Figure 2, respectively, and F
The bit area represents a storage unit designation bit area, the n-bit area represents an address designation bit area within a storage unit, and 8 represents an explanatory block for explaining processing for dealing with an increase in storage unit capacity.

Now suppose that the number of intra-unit addresses in one storage unit is 2.
If there are two storage units, the floating memory address conversion memory 6 is accessed using the F bit of the address information set in the address register 1.

As a result, storage unit instruction information (MSU AI and BAN
KA) is read out, and the decoder 7 supplies an enable signal to the storage unit.

This is no different from what was explained in connection with FIG.

In the above, it is assumed that the capacity of one storage unit is increased to increase the number of addresses within the unit to 2(n+1), and as a result, the number of storage units becomes 2(F-1).

In this case, as shown in the second block from the top of block 8 shown in FIG. 3, 1 bit X in the F bits is added to n bits of the address within the storage unit to access the address within the storage unit.

At this time, regardless of whether the bit X is "O" or "1", the storage unit instruction information (MSU A, BAN A:) read from the memory 6 is made to be the same.

In other words, the contents of address “**...*0” in memory 6 and “*
*...*1" should be the same as the contents of the address.

By doing so, it is possible to easily deal with an increase in the number of addresses within a storage unit.

Needless to say, the number of addresses within a storage unit is 2 (
Even if the number increases to n+2) or 2(n+a), the same steps can be taken.

In addition, as shown in Figure 1, the floating address
Even when register 3 is used, it is possible to adopt a similar method.

However, in this case, it is necessary to change the number of bits set in register 3, and it is necessary to take measures to ignore bit X during comparison processing by comparator circuit 4. It is easy to make mistakes.

As explained above, according to the present invention, compared to the conventional floating memory addressing method using registers, the hardware configuration is greatly simplified, and the configuration of the storage device can be easily changed. I can handle it.

[Brief explanation of drawings]

FIG. 1 shows an example of a conventional system, FIG. 2 shows an example structure representing the overall concept of the present invention, and FIG. 3 explains an aspect of dealing with an increase or decrease in the capacity of a storage unit when used in the present invention. An explanatory diagram is shown. In the figure, 1 is an address register, 2 is a write/unique module, 5 is a storage bank, 6 is a floating memory/address conversion memory, and 7 is a decoder.

Claims (1)

[Claims] 1. A storage device having a plurality of storage units that can be accessed independently, and selecting the storage unit based on one or more bit information in given -r address information, and In a memory access processing method in which the correspondence between the bit information and the storage unit is made variable, an address position is provided in a one-to-one correspondence with the bit information in the address information, and the storage unit is located at the address position. A floating memory/address conversion memory is provided in which designation information specifying one of the above is stored in a rewritable manner, and the storage unit is selected based on the contents read from the floating memory/address conversion memory, and the storage unit within the storage unit is selected. According to the number of address positions, some bits of the bit information in the address information can also be used as address information for selecting the address position, and in the floating memory/address conversion memory. The memory is characterized in that the same designation information that designates the pupil unit is stored in a plurality of address positions that differ only in some of the bits of the bit information.
Access processing method. 2. The memory access processing method according to claim 1, wherein the floating memory address conversion memory includes a mounting/non-mounting instruction flag for the storage unit in the specification information.