JPS5847787B2 - magnetic bubble cassette memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a magnetic bubble memory using a cassette containing bubble memory chips with major and minor loops.

A major-minor type magnetic bubble memory chip includes a large number of minor loops, for example, 140 minor loops, and a common major loop among these loops on a magnetic substrate, and each loop also includes a large number of transfer magnetic patterns.

Therefore, some minor loops may have problems such as bubble transfer failure or abnormal bubble generation due to crystal defects in the substrate, defective shape of the magnetic pattern, etc.

To deal with this kind of case, create a large number of minor loops, for example 140 as shown above, but actually create 12.
It is preferable to use 8 of them and use the remaining 12 for excluding defective loops.

According to this method, if the number of defective loops is 12 or less, the chip can be used as a normal chip, and the address of the defective loop of each chip is stored in the FROM of the device that houses the read/write control circuit for the chip. It is sufficient to write , and then avoid using the defective loop.

In bubble memory where the device and chip are permanently connected, minor loop defects can be dealt with using the above method, but in cassette type bubble memory, the device and memory chip are arbitrarily connected and separated, so the memory chip is attached to the main device side. It is pointless to provide a FROM to store defective minor loops.

Although it is conceivable to provide a FROM on the memory chip, this would inevitably increase the number of terminals on the chip and increase costs.

In view of these points, the present invention is a magnetic material that enables recording and displaying of defective loops without complicating the structure and therefore without increasing costs, and that enables the use of memory cassettes with the defective loops excluded. It attempts to provide bubble memory.

The present invention relates to a magnetic bubble memory in which a cassette containing a bubble memory chip having a major minor loop is set in a main unit for read/write operation, in which any portion of the minor loop of the bubble memory chip is replaced by a defective minor loop. The main unit is equipped with a storage unit that stores the address of the defective minor loop, a detector that detects insertion of a cassette into the main unit, and a detector that detects power on. The present invention is characterized in that it is provided with a control circuit that reads a defective minor loop address from the cassette and writes it to the storage section when the cassette is loaded.This will be described in detail below with reference to the drawings.

FIG. 1 shows a cassette containing a bubble chip, where 1 is a bubble chip attached to a substrate 2, 3 is a drive coil that provides a rotational driving magnetic field to the chip, 4 is a permanent magnet that provides a bias magnetic field to the chip, and 5 is a permanent magnet that provides a bias magnetic field to the chip. is its yoke.

A connector 6 includes a plurality of pins 7 connected to various terminals of the chip 1 and the coil 3.

As shown in FIG. 2, the bubble chip includes a large number of minor loops 11 and a common major loop 12.

A bubble generator 13, a bubble detector 14, etc. are provided in the major loop, and a transfer gate 15 is provided between the major loop and the minor loop.

The bubble generator 13 generates or does not generate bubbles according to the input data, and as a result, a string of bubbles is created that is present or absent corresponding to 1 or 0 of the input data.

Furthermore, the minor loop 11 is provided every predetermined bit of the major loop 12, for example, every two bits, and therefore there is a predetermined bit (in this example, one empty bit) between the minor loops, and the bubble generator corresponds to this empty bit. The position does not generate bubbles.

Therefore, the bubble train sent from the bubble generator 13 to the major loop 12, as shown in FIG. 3, consists of information bits ○, which are present or absent depending on the data, and empty bits intervening between the information bits.

A bubble string with a certain structure, for example, a minor loop 124
When using 124 information bits (this constitutes 1 information block) and 123 empty bits interposed between them, the head of the bubble string is bubble generator 1.
When the most downstream minor loop is reached as viewed from 3, the transfer gate 15 opens, and the information bits are transferred from the major loop to each minor loop all at once.

Thereafter, similar operations are repeated, and information bits are sequentially written into each of the minor loops 11.

Reading is the opposite; when each information block written across a large number of minor loops reaches the transfer gate 15, the gate is opened, and the information block is transferred from each minor loop to the major loop all at once. It then passes through a measure loop and is led to a bubble detector 14, which detects bubbles and outputs an electrical signal.

If a loop with a memory chip, for example 11a, has a defect such as bubble disappearance or abnormal bubble occurrence in N, the entire chip becomes unusable in S, so the defective loop is separated and only other normal loops are left. It is better to use L.

This separation can be performed by using the address of the defective minor loop as an empty bit, similar to the empty bit between loops, and not writing information thereto.

That is, as shown in FIG. 4, the write control uses an address counter 21, a storage section 22 for storing the address of the defective minor loop, and a comparator 23. In this example, the clock CLK synchronized with the bubble 1 driving magnetic field is /2 The count value of the address counter 21 that counts the frequency division output is the address of the defective minor loop (simply, this is the address of the most downstream minor loop seen from the bubble generator with 1 and one free bit placed there). The address of the minor loop in front is 2...
...), the comparator 23 generates a match output "0", the gate 24 is closed, and a bubble is generated according to the theta. It is only necessary to prohibit the output of the permission signal Sg.

As a result, no bubble is generated at the time point (address) corresponding to the defective minor loop, and the bubble generation for the data is extended to the time point corresponding to the next minor loop.

The match output of the comparator 23 is also sent to the storage unit 22, and the address of the next defective loop is output, and by performing the same operation, data can be written only to the normal minor loops, avoiding all defective minor loops of the cassette. It becomes possible.

As mentioned above, FROM (
The method of providing a programmable read-only memory and storing data in the memory is difficult to implement with a cassette type.

Therefore, in the present invention, the address of the defective minor loop is stored in the minor loop of the memory chip of the cassette, and the main unit has RAM (random access memory).
The address of the defective minor loop is read from the cassette when the cassette is inserted and when the power is turned on.
A control circuit for storing the information in M is provided.

FIG. 5 shows an example thereof. In this figure, l・1 above the chain line
The cassette 10 side is shown, and the bottom side shows the main unit 30 side.

31 is the above-mentioned RAM, 32 is the same control circuit, and 33 is a write/read control circuit.

Although not shown in detail, the control circuit 32 includes a cassette insertion detector 34 and a power-on detector 35 into the main unit 30, and when there is an output from either of these, the control circuit 33
is activated to read the address of the defective minor loop from the cassette 10 and write it to the RAM 31.

One of the minor loops 11, 1lb, is an address storage loop, and the remaining 11c is a data storage loop, and the address storage loop 1lb is an address in the data storage loop 11c, that is, a group of information written in these loops. Information indicating the number of bits of an arbitrary information bit from the reference information bit is written based on the bit.

The defective minor loop address may be written to the minor loops 1lb and 11c by any appropriate method, but it is preferable to write the defective minor loop address to a certain address (this is assumed to be X) represented by the address storage loop 1lb of the data storage loop 11c. It's convenient.

Alternatively, the information written to the loop 1lb may be one bit indicating the position of the reference information bit 1 (the address can be obtained by counting clocks from the bit), so
The address of the defective loop may be written into this loop 1lb.

If the defective minor loop address is written into the RAM 31 at the same time as the cassette is inserted, it is convenient that the cassette becomes ready for general use immediately after insertion.

Further, since the RAM loses its stored contents when the power is turned off, there is an advantage that if the power is turned on and the defective loop addresses of the memory chips of all the cassettes installed in the main unit are read, the cassettes are immediately put into use.

As explained in detail above, according to the present invention, the main body device includes:
It is possible to insert any cassette, not limited to a specific one, and immediately use the part of the cassette to store and play, contributing to cost reduction and expansion of the range of application of cassette type magnetic bubble memory. It's thick where it is.

[Brief explanation of the drawing]

Fig. 1 is an explanatory diagram of a bubble memory cassette, Fig. 2 is an explanatory diagram of a major/minor set bubble memory, Fig. 3 is an explanatory diagram of the structure of information blocks, and Figs. 4 and 5 are examples of the present invention. It is a block diagram explaining. In the drawing, 1 is a bubble memory chip, 10 is a center, 1
1 is a minor loop, 12 is a major loop, 11a is a defective loop, 31 is a storage section, 32 is a control circuit, 34 is a cassette insertion detector, and 35 is a power-on detector.

Claims (1)

[Claims] 1. In a magnetic bubble memory in which a cassette containing a bubble memory chip with a major minor loop is set in the main unit and read/write driven, any part of the minor loop of the bubble memory chip is set to the address of the defective minor loop. It is also equipped with a storage section on the main unit side that stores the address of the defective minor loop, a detector that detects insertion of a cassette into the main unit, and a detector that detects when the power is turned on. A magnetic bubble cassette memory comprising: a control circuit for reading a defective minor loop address from the cassette and writing it to the storage section.