JPS5847890B2 - flip-flop circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to flip-flop circuits, and more particularly,
The present invention relates to effective means for realizing a frequency divider circuit that can operate each human output line with a single gate.

Conventionally, so-called master-slave flip-flops are known that use two input control gates and two RS flip-flops for binary counters and frequency divider circuits.

As shown in FIG. 1, it is a circuit formed by connecting dotted frames 1 and 2.

The operation of this circuit will be explained as follows.

That is, first, two clock pulses CP and CP are input signals.

When CP is at a high level (hereinafter referred to as H), CP is at a low level (hereinafter referred to as L), and conversely, when CP is at L, CP is at H.

Assuming that the output Q2 is now H and CP becomes H, the input control gates A and B are opened and the output Q1 of the left RS flip-flop becomes H.

Next, when CP becomes L, gates A and B are closed.

Then, CP becomes H, input control gates E and F open, and the right RS flip-flop is inverted by Q1.
Its output Q2 becomes L.

Furthermore, CP becomes L and control gates E and F are closed.

In this way, by the clock pulses CP, CP,
Exchange the state of H with the left and right RS flip-flops, and
Every time the P pulse goes high twice, Q2 goes high once.

This is the basic operation of this circuit, but there are some drawbacks.

For example, the number of gates is as large as 8. There are two input and output lines each, which hinders high-density integrated circuits.

Furthermore, there are restrictions on the waveforms of CP and CP, and there must be no portion where both are at H.

The present invention has been made in view of the above points, and realizes the same function as the flip-flop circuit described above by using one signal line for each of four gate inputs and outputs, and achieves high integration and high speed operation. The present invention provides an integrated circuit that is capable of

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to drawings based on one embodiment.

FIG. 2 is a circuit diagram of an embodiment of the present invention, and FIGS. 3 and 4 are plan views of the integrated circuit.

In Fig. 3, two collectors of gates t-G1 and G3 shown in Fig. 2 are used in parallel, and in Fig. 4,
The areas of collectors 12 and 32 are made larger than those of collectors 11 and 31.

The diagonally shaded base regions of G1-G1 and G4 are metal-semiconductor contact diodes (Schottky diodes) formed using a metal such as titanium.

Next, the operating principle of this embodiment will be explained with reference to the signal waveform diagram shown in FIG.

First, assume that the third gate of the flip-flop at the front stage is 03' and the pace signal waveform is as shown in FIG.

Assuming that the signal 03' is initially L, the signal line coupled from the previous stage to the stage of interest becomes floating, and one of the gates G1 and G2 is ON and the other is OFF.

Let us now assume that the input terminal of G1 is H and that of 02 is L.

Then, 02 becomes an L voltage lower than 01 by the forward rising voltage vF of the diode.

The input terminal of G3, which is the output terminal of G1, is at L level, and the input terminal of G4 is also higher than this by ■F, which is not the voltage required to turn G4 ON, but is still at L level.

Next, when the input signal of 03' becomes H, the input terminal of G2 becomes almost zero, that of G1 becomes vF and both become L, and G1, G
The signal lines from 2 to G3 and G4 are floating,
Since the force at the input end of G4 was at a potential higher than that of G3 by vF, G4 became H first, and as a result, G3 became low at vF.
settle down to the level.

Furthermore, if 03' becomes L, G4 will turn ON.
In this state, the input terminal of G1 cannot become high, the input terminal of G2 becomes H level, and the input terminal of G1 becomes zero (L).

As a result, the input terminal of G4, to which the output terminal of G2 is connected, becomes zero (L), and as a result, the input terminal of G3 becomes H.

Next, when G3' becomes H again, the input terminal of 02 becomes zero L,
The input terminal of G1 becomes L of vF.

At this time, the output ends of G1 and G2 are floating, so G3 and G4 maintain their states.

Further, when G3' becomes L, the input terminal of G1 which was at ■F becomes H before the input terminal of G2 which was at zero, and G2 becomes L of vF.

As a result, the input terminal of G3 is zero L, and that of G4 is vF
becomes L and returns to the original state.

In this way, every time the input terminal of 03' becomes H by 2 degrees, the input terminal of 03 becomes H by 1 degree, and frequency division by 2 is realized.

If each of the output terminals of G3', Gl, and G3 is
2, G3, G2"(G2" is the second gate of the next stage of the flip-flop in question) is not larger in area than each other output terminal, and at the same time,
Assuming that they are not connected to the remaining output terminals of each, when the gates of 03', G1, and G3 are turned on, the input terminals of 02, G3, and G2'' in the next stage cannot be brought to a sufficiently low level. Otherwise, accurate frequency division operation will not be performed.

As described above, according to the present invention, frequency division by two operation can be realized by using one input/output line each and four gates. Therefore, an integrated circuit with high integration density can be constructed, and the logic width can be reduced. Since a portion of the circuit is narrowed by vF, fan-out is small, and the number of gates is small, high-speed operation with low power consumption is possible.

FIG. 6 shows an application example in which the logic width of many parts is narrowed by vF.

That is, a diode is coupled in a forward direction from terminal 2 of gate G2 to terminal 1 of gate G1, and another diode is coupled in a forward direction from terminal 3 of gate G3 to terminal 4 of gate G4. is connected.

In this circuit, instead of connecting the two output terminals of each of gates G1 and G3, the area of the output terminal of each 1 is made larger than the area of the remaining output terminal, and the plan view is when it is integrated into an integrated circuit. FIG. 7 shows the signal waveform, and FIG. 8 shows the signal waveform.

The operating principle is the same as the above application example, but G2 and G4
It can be seen that the effect of the diode added to the diodes has narrowed the logic width in more parts.

This enables faster operation with lower power consumption.

In the example of FIG. 6, the area of the output end connected to terminal 4 of gate G2 is wider than the other output ends of the same gate, or the area of the output end connected to terminal 4 of the gate G2 is larger than that of other output ends of the same gate as shown by the broken line in the figure. The area of the output terminal connected to the terminal 2 of the gate G4 is larger than the area of the other output terminal of the same gate, or the area of the output terminal connected to the terminal 2 of the gate G4 is larger than that of the other output terminal of the same gate, as shown by the broken line in the figure. It can also be configured to be connected to

[Brief explanation of the drawing]

FIG. 1 is a conventional mask slave flip-flop circuit, and FIG. 2 is a circuit diagram for explaining an embodiment of the present invention.
Figures 3 and 4 are plan views of the integrated circuit;
Figure 5 is a timing chart diagram to explain its operating principle, Figure 6 is a circuit diagram showing another application example, and Figure 7 is a plan view when the circuit in Figure 6 is transformed into an integrated circuit. 8 are timing charts thereof.

Claims (1)

[Claims] 1. At least four logic gates each consisting of a first type transistor having an inverted structure and a second type transistor supplying power thereto, the first output terminal of the first logic gate; is the input terminal of the second logic gate, and the first terminal of the second logic gate
The output terminal of the first logic gate is the input terminal of the first logic gate and the first output terminal of the fourth logic gate, and the first output terminal of the second logic gate is the input terminal of the fourth logic gate and the first output terminal of the fourth logic gate. and a second output terminal of the first logic gate are connected to an input terminal of the third logic gate and a second output terminal of the fourth logic gate, respectively, and the input terminal of the first logic gate is connected to the second output terminal of the first logic gate. A first diode is interposed in a forward direction toward the input end of the logic gate, and a second diode is interposed in a forward direction toward the input end 3 of the third logic gate from the input end of the fourth logic gate. a diode is interposed between the second logic gate and the first logic gate.
A third output terminal of the same logic gate is connected to the output terminal of
A flip-flop circuit characterized in that a third output terminal of the third logic gate is connected to a second output terminal of the third logic gate. 2. At least four logic gates each consisting of a first type transistor having an inverted structure and a second type transistor supplying power thereto, the first output terminal of the first logic gate being connected to the second type transistor. the input terminal and the first terminal of the second logic gate.
The output terminal of the first logic gate is the input terminal of the first logic gate and the first output terminal of the fourth logic gate, and the first output terminal of the second logic gate is the input terminal of the fourth logic gate and the first output terminal of the third logic gate. and a second output terminal of the first logic gate are connected to an input terminal of the third logic gate and a second output terminal of the fourth logic gate, respectively, and the input terminal of the first logic gate is connected to the second output terminal of the first logic gate. A first diode is interposed in a forward direction toward the input end of the logic gate, and a first diode is interposed in a forward direction toward the input end 3 of the third logic gate from the input end of the fourth logic gate. 2 diodes are interposed, the area of the second output terminal of the first logic gate is larger than the first output terminal of the same logic gate, and the area of the second output terminal of the third logic gate is
A flip-flop circuit characterized in that the flip-flop circuit is wider than the first output end of the same logic gate.