JPS584813B2 - Mesagata hand taisouchinoseiho - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a mesa-type semiconductor device, particularly a mesa-type semiconductor device in which the surface of a semiconductor substrate where a PN junction is exposed is covered with a passivation film, such as a passivation film. Concerning the manufacturing method.

Mesa-type semiconductor devices, such as mesa-type diodes and mesa-type power transistors, can achieve higher breakdown voltage than planar-type semiconductor devices, and can provide greater output with the same semiconductor pellet size. In addition, at least one junction is formed as a flat junction over the entire area of the semiconductor substrate during manufacturing, and selective diffusion or the like is not required. Compared to the planar type, manufacturing is simplified because the formation of a diffusion mask associated with this selective diffusion, etc., and the extremely complicated process of photo-etching to open a window for this mask can be reduced by at least one step compared to the planar type. It has the advantage of being

However, in this mesa type semiconductor device, when a passivation film is formed to cover the PN junction exposed on the semiconductor surface, for example, the junction surface exposed on the side surface of the mesa groove or the top surface of the mesa, After the formation of the mesa groove, i.e.
Since it is necessary to form this passivation film in a state where at least a flat junction crossed by a mesa groove has already been formed, high-temperature heating is not required when forming this passivation film. It causes fluctuations in the impurity concentration distribution and affects the characteristics.

Therefore, in the mesa-type semiconductor device, it is not preferable to form this passivation film by thermal oxidation of the semiconductor surface, and it is preferable to form it by chemical vapor deposition at a relatively low temperature. desirable.

On the other hand, as a passivation film, SiO
2.Si3N4 or resins are used, but they have a large difference in coefficient of thermal expansion from the semiconductor substrate, have problems with moisture resistance, and SiO2, for example, lacks the blocking effect against sodium ions and is not an insulating material. Since it is a body, it has the disadvantage of having a memory effect, and has the disadvantage of being somewhat unreliable.

As a passivation coating free of such drawbacks, at least the layer deposited on the semiconductor substrate may be a semi-insulating coating, such as a polycrystalline or amorphous layer of high-purity silicon or oxygen-doped silicon. It has come to be proposed that the formation of

Furthermore, in a mesa-type semiconductor device in which a passivation film is formed in this way, when an electrode window is formed in the passivation film by photo-etching, severe unevenness due to mesa grooves is formed on the surface of the semiconductor substrate. Because of this, even if a photoresist is formed by the usual spin coating method during photoetching, the photoresist will not be coated to a sufficient thickness on the shoulder of the mesa, and then the photoresist will be exposed to light. If the above-mentioned passivation film is etched by developing and patterning it and using it as an etching mask, the shoulders of the mesa will not be sufficiently masked, and the passivation film in this area will be etched away, leaving the semiconductor substrate exposed. This has the disadvantage that the surface is not sufficiently protected and reliability is reduced.

The present invention aims to provide a method for manufacturing a mesa-type semiconductor device, which makes it possible to obtain a highly reliable semiconductor device of this type without causing the above-mentioned drawbacks.

First, the process for obtaining a mesa diode, for example a varicap, will be explained with reference to FIG.

As shown in FIG. 1A, a semiconductor substrate 1 is provided, and first and second mask layers 2 and 3 are laminated and deposited on at least one main surface thereof.

The semiconductor substrate 1 is made of, for example, a silicon substrate, and includes an N-type semiconductor layer having a relatively low impurity concentration and a P-type semiconductor layer formed entirely thereon by diffusion or epitaxial growth. It has a structure in which a flat PN junction J is formed along the above-mentioned one main surface of the semiconductor device.

Further, the first and second mask layers 2 and 3 deposited on the substrate 1 are those that are difficult to be attacked by the etching solution for the substrate 1 and have different etching characteristics, that is, the mask layers 2 and 3 are difficult to be attacked by the etching solution for the mask layer 2. The mask layer 3 is made of a material having a sufficiently slow etching rate so that the mask layer 3 is not attacked.

As a mask layer having such characteristics, mask layer 2
SiO2 can be used as the mask layer 3, and Si3N4 can be used as the mask layer 3.

As shown in FIG. 1B, the mask layers 2 and 3 are sequentially selectively etched to remove the portions of the base 1 where the mesa grooves are to be formed.

Next, as shown in FIG. 1C, selective etching is performed on the upper mask layer 3, leaving only the portion on which the electrode window is to be formed and etching away the other portion.

In this case, the outer periphery of the mask layer 3 is made to extend inward from the outer periphery of the mask layer 2 by a required width W.

Thereafter, as shown in FIG. 1D, mesa etching is performed on the base 1 using the mask layers 3 and 2 as etching masks to form a mesa groove 4 having a depth that crosses the junction J.

In this case, the mesa groove 4 is formed by side etching so as to extend below the mask layer 2 with a width ω.

Next, as shown in FIG. 1E, using the second mask layer 3 as a mask, the first mask layer 2 below it is etched, and not only the portions not covered by the mask layer 3 but also the portions not covered by the mask layer 3 are etched. Etching is performed to penetrate under the periphery of the mask layer 3 with a required width Wo by over-etching to form the eaves 5.

Thereafter, as shown in FIG. 1F, a semi-insulating passivation film 6 is formed by chemical vapor deposition at a relatively low temperature.

In this way, the passivation film 6 is deposited on the surface of the base 10 except for the portion under the eaves 5 of the mask layer 3 and the portion having the mask layer 2.

In this case, the coating 6 is also formed on the mask layer 3, but the sum of the thickness t of the mask layers 2 and 3 and the width Wo of the eaves 5
By appropriately selecting in advance according to the thickness of the coating 6, the coating 6 is made to form a step 7 between a portion on the layer 3 and another portion.

This semi-insulating film 6 is formed by chemical vapor deposition (hereinafter referred to as CVD).
For example, a high-purity polycrystalline silicon layer formed by thermal decomposition of silane SiH4 at 650°C, or S
It is composed of a polycrystalline silicon layer doped with oxygen using iH4 and, for example, N20, NO, NO2, or the like.

The semi-insulating film 6 made of polycrystalline silicon thus formed has extremely superior adhesion to the substrate 1 compared to, for example, SiO2 or Si3N4 formed by CVD.

In addition, when forming the film 6 of polycrystalline silicon layer by such CVD method, the thickness is desirably selected to be 0.2 μm or more, preferably 0.5 μm or more for the purpose of passivation. As mentioned above, step 7
For example, the thickness of the mask layer 2 should be set to 1.0μ.
m or more, the thickness of the mask layer 3 is 0.1 μm or more, and the layer 2
The over-etching amount, that is, the width Wo is approximately 2 of the thickness of layer 2.
More than twice as much.

Incidentally, when the eaves 5 is not formed, the above-mentioned CV
The height of the step that causes the step break in the polycrystalline silicon layer by method D needs to be 3 to 4 times the thickness of the coating 6, that is, the polycrystalline silicon layer, and it is necessary to form such a thick mask layer on the substrate 1. Doing so not only causes operational problems, but also causes undesirable effects due to heat such as thermal distortion.

Thereafter, as shown in FIG. 1G, the mask layer 2 is etched away, the mask layer 3 and the coating 6 thereon are removed, and an electrode window 8 is formed here.

In this case, the etching for the mask layer 2 is performed by etching the coating 60.
Since the process is performed through the step cut 7, layer 2 can be reliably and quickly removed.
can be removed.

Next, as shown in FIG. 1H, an electrode 9 is ohmicly deposited on the semiconductor region (P-type region in the illustrated example) exposed on the base 10 and mesa 10 through the electrode window 8.

In this way, a mesa-type semiconductor device 11 is constructed in which a semi-insulating passivation film 6 is formed on the surface of the base 1 including the inner surface of the mesa groove 4 where the junction J faces.

Incidentally, in the mesa-type semiconductor device 10 obtained in this way,
The process described in connection with FIG. The width W between the periphery of the mask layer 3 and the periphery of the mask layer 2 is selected, and this width W is selected to be, for example, 10 μm or more.

The example illustrated in FIG. 1 has one junction J, with mesa 10
In the case of obtaining a varicap on which one electrode 9 is formed, for example, a mesa having another junction on the mesa 10 and forming an electrode on each of two or more semiconductor regions facing on the mesa 10 is used. An example of obtaining a type transistor will be described with reference to FIG.

In this example, parts corresponding to those in FIG.
However, on the semiconductor layer 1a having a high impurity concentration of N type, for example, which constitutes the low resistance region of the collector, a semiconductor layer 1b of the same conductivity type and having a low impurity concentration, which constitutes the high resistance region of the collector, is removed. When a semiconductor layer 1c of another conductivity type, for example Hp type, constituting a base region is formed over the entire surface to form a collector junction, a PN junction J is formed flat along the surface direction of the base 1, A diffusion region 1d serving as an emitter region of a different conductivity type, for example, P type, is selectively formed on the layer 1c to form an emitter junction JE.

As shown in FIG. 2A, mask layers 2 and 3 are deposited on the surface of this substrate 10 in the same manner as described with respect to FIG. 1A.

Then, as shown in FIG. 2B, selective etching is performed on the mask layers 2 and 3, leaving the part having the region 1d and its surroundings to a required width, and forming mesa grooves in other parts. The portion is removed as described for FIG. 1B.

Next, as shown in FIG. 2C, selective etching is further performed on the mask layer 3 to finally form a portion on the mesa where an electrode is to be formed, that is, a portion on the region 1d where an emitter electrode is to be formed. The remaining portions of the mask layer 3 are removed by etching, leaving only the portion on the upper semiconductor layer 1c where the base electrode is to be formed.

In the illustrated example, a mask layer 3d is formed in the form of an island on the region 1d, and a mask layer 3C is formed in the semiconductor layer 1c in an annular shape surrounding the mask layer 3d with a required interval maintained around it.

In this case as well, the outer circumferential edge of the outer mask layer 3c is positioned inward from the outer circumferential edge of the mask layer 2 with a required width W, similar to the embodiment described above.

Next, as shown in FIG. 2D, using the mask layer 2 as a mask, mesa etching is performed on the substrate 1 in the same manner as described in FIG. A mesa 10 having a region 1d is formed by a mesa groove 4.
form.

Thereafter, as shown in FIG. 2E, the mask layer 2 is over-etched in the same manner as described in FIG.
o forms a protruding eaves 5.

Thereafter, as shown in FIG. 2F, a high-purity polycrystalline silicon layer or an oxygen-doped polycrystalline silicon layer is produced by the CVD method in the same manner as described in FIG. 1F, and a passivation film 6 is formed. form.

In this case as well, by appropriately selecting the sum t of the thicknesses of the mask layers 2 and 3 and the protrusion width WO of the eaves 5, the film 6 can be formed on the portions 3d and 3c of each mask layer 3. A step cut 7 is formed between the portion formed directly on the base L and the portion directly formed on the base L.

Next, as shown in FIG. 2G, in the same manner as described in FIG. An emitter electrode window 8d is formed on the region 1d, and an annular base electrode window 8c is formed on the surrounding semiconductor layer 1c.

Next, as shown in FIG. 2H, an emitter electrode 9d and a base electrode 9c are formed on the region 1d, that is, the emitter region, looking into the top surface of the mesa 10 of the base body 1 through the windows 8d and 8c, and on the semiconductor layer 1c, that is, the base region, respectively. is applied to Ohmitsuku.

In this way, the mesa type transistor 21 is formed in which the surface of the collector junction J extending into the mesa groove 4 and the surface of the emitter junction JE extending to the top surface of the mesa 10 are each covered with a semi-insulating passivation film 6. configured.

As described above, according to the manufacturing method of the present invention, a passivation film 6 made of a semi-insulating polycrystalline silicon layer or the like, such as a polycrystalline silicon layer doped with O, is formed on a semiconductor, for example, a silicon substrate 1. Because of this, it is possible to avoid the memory effect due to the charge accumulation effect as mentioned at the beginning, and when forming the electrode window, it is possible to remove the mask layer 2 instead of using photoetching as in the conventional method. Therefore, a highly reliable mesa-type semiconductor device can be obtained without causing shoulder breakage or the like in the passivation film 6.

Moreover, as mentioned above, the semi-insulating passivation film 6
When using a high-purity polycrystalline silicon layer, its specific resistance is 105 to 107 Ωcm;
When using a polycrystalline silicon layer doped with 0 atom % or more, the resistance can be set to 10 7 to 10 9 Ωcm.

Therefore, for example, when trying to obtain a mesa transistor with a high hFE, the passivation film 6 that extends over the junction Je, that is, between the emitter base and the emitter base, should have a high Preferably, a resistive oxygen-doped polycrystalline silicon layer is used.

In the above example, the passivation film is formed of a single layer of polycrystalline silicon, but as shown in FIGS. Coating 6 consisting of a gyricon layer
It is also possible to have a multilayer structure in which A is formed and a coating 6B made of polycrystalline silicon or Si3N4 layer doped with nitrogen N is formed thereon by the CVD method.

This layer 6B is formed by the above-mentioned CVD method, using NH3 instead of N2O, NO, and NO2 as an oxygen supply source, and sending it together with SiH4 to form a polycrystalline silicon layer or Si3N4 doped with N.

Note that this N-doped polycrystalline layer contains 57ato
When doped with m% or more, its specific resistance is 5×109Ωcm
That's all.

When forming the N-doped polycrystalline silicon layer or SiN4 layer 6B in this way, it is possible to further improve the moisture resistance of the passivation film 6 and obtain a highly reliable semiconductor device. , electrodes 9, 9d, 9c
There is an advantage in that it can be selectively formed by, for example, Ni plating.

That is, since Ni plating is not generated on the N-doped polycrystalline Si layer or Si3N4 layer, this serves as a mask to selectively form electrodes only on the Si substrate exposed through the windows 8, 8d, and 8c. can do.

In order to improve the adhesion between the base 1 and each electrode, in some cases, the base surface exposed through the windows 8, 8d, and 8c may be coated with K.
The surface can also be roughened by OH treatment.

In the above example, the present invention was explained using a mesa type diode (paracap) and a transistor, but the present invention can also be applied to other semiconductor devices such as integrated circuits.

[Brief explanation of drawings]

1A to 1H are enlarged cross-sectional views of each step showing an example of the manufacturing method of the present invention, FIGS. 2A to H are enlarged sectional views of each step showing another example of the manufacturing method of the present invention, and FIGS. 3 and 4 The figures are enlarged cross-sectional views of mesa-type semiconductor devices obtained by other examples of the manufacturing method of the present invention. 1 is a semiconductor substrate; 2 and 3 are first and second mask layers;
4 is a mesa groove, 10 is a mesa, J and JE are PN junctions, 5 is an eaves, 8, 8d, and 8c are electrode windows, and 9, 9d, and 9c are electrodes.

Claims (1)

[Claims] 1. On the one main surface of the semiconductor substrate in which the PN junction surface is formed along one main surface, first
forming a mask layer and a second mask layer such that the outer periphery of the second mask layer as an upper layer is located inside the outer periphery of the first mask layer as a lower layer by a predetermined width; , performing mesa etching on the semiconductor substrate using the first mask layer as an etching mask; over-etching the first mask layer using the second mask layer as a mask; A mesa-type semiconductor device comprising: a step of depositing a passivation film; and a step of selectively removing the passivation film by removing the first mask layer. manufacturing method.