JPS5848943B2 - Information processing equipment with usage rate monitoring function - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an information processing device having a usage rate monitoring function.

Conventional techniques for measuring the usage rate of information processing equipment (hereinafter referred to as CPU usage rate) include: ■ Measuring technology using an attached jig (no-ware counter or hardware monitor); ■ Measuring technology using a CPU in a register.
Accumulate idle time and programmatically read registers.
There is a technique to measure by lighting.

With the conventional technology, it is not possible to know the CPU usage status with a program, and with the previous technology, although it is possible to know the CPU usage rate with a program, it is difficult to monitor the state where the CPU usage rate is above or below a certain value. is CP at each measurement time interval.
It is necessary to access the register in which the idle time of U is accumulated, which is a problem because it adds extra overhead to the system.

The load given to an electronic computer system includes high-priority work and low-priority work.

The amount of work each person does changes from moment to moment.

Therefore, an object of the present invention is to notify a program of a high load or low load state of the CPU by generating a CPU interrupt when the CPU utilization rate becomes more than or less than a certain set value. When necessary, the program automatically changes the configuration of the load on the system, such as temporarily suspending low-priority work and adding low-priority work to the system when the CPU is under low load. It provides functionality.

The feature of the present invention is that the measurement time interval value and the upper and lower limits of the CPU usage rate during the measurement time interval can be set by a program, and the CPU usage rate during the measurement time interval is the set value. When it is above the upper limit or below the lower limit, C
This is to generate a PU interrupt and notify the program.

Next, embodiments of the present invention will be described in detail using the drawings.

FIG. 1 shows a system diagram of a CPU utilization rate automatic measurement and notification device which is an embodiment of the present invention.

Register 1 is an accumulation register that is counted up by +1 each time the IDLE instruction is executed.

Register 2 is an accumulation register that is counted up by +1 by a time generator, and is used to synchronize with the measurement time interval.

Register 3 is a register in which a measurement time interval value is set and is set by a program.

Register 4 is a value obtained by converting the IDLE time into the number of IDLE command executions, and the lower limit of the number of IDLE command executions is set by the program.
The upper limit of the number of instruction executions is set by the program.

Registers 1 and 4 are connected to comparison circuit 6, and registers 1 and 5 are connected to comparison circuit 7.

Registers 2 and 3 are connected by a comparison circuit 8, comparison circuits 6 and 8 are connected to an AND circuit 9, and comparison circuits 7 and 8 are connected to an AND circuit.
Connected to D circuit 10.

Comparison circuit 8 is connected to delay circuit 11 and register 2,
Delay circuit 11 is connected to register 1 .

Next, the operation of this embodiment will be explained.

By comparing the registers 2 and 3 with the comparison circuit 8, the measurement time intervals are synchronized, and when synchronization is achieved, the connection lines to the AND circuits 9 and 10 are turned on.

At this time, the comparison circuit 6 of registers 1 and 4 or the register 1
If the connection line from the comparison circuit to the AND circuit of O
Since it is N, an interrupt occurs at this time due to the output of AND circuit 9 or 10.

Further, when the comparison circuit 8 synchronizes the measurement time intervals, the register 2 is reset and at the same time, the register 1 is also reset through the delay circuit 11.

With the configuration as described above, the following effects can be obtained in the present invention.

(1) The configuration of the load applied to the computer system can be dynamically changed by an interrupt caused by the CPU itself when the CPU utilization rate becomes more than or less than the value set by the program.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention. Explanation of symbols, 12 first counter, 2: second counter, 3: time interval setting register, 4: lower limit value setting register, 5: upper limit value setting register, 6 to 8: comparison circuit, 9 to 1
0: AND circuit, 1,1: delay circuit.

Claims (1)

[Claims] 1. A first counter that counts non-operating time, a second counter that counts elapsed time, a time interval setting register that can set a desired time interval, and the contents of the second counter are set as a time interval setting register. means for outputting a time interval signal when the value of the non-operating time is reached; an upper limit value setting register capable of setting the upper limit value of the non-operating time; a lower limit value setting register capable of setting the lower limit value of the non-operating time; When the signal is output, a first interrupt signal is issued when the contents of the first counter reach the value of the upper limit value setting register, and a second interrupt signal is issued when the content of the first counter reaches the value of the lower limit value setting register. What is claimed is: 1. An information processing device having a usage rate monitoring function, comprising: means for changing the work load structure according to the priority order based on the first and second interrupt signals.