JPS5849026B2 - Multilayer wiring manufacturing method - Google Patents

Description

[Detailed description of the invention] The present invention relates to a method for manufacturing multilayer wiring.

In order to achieve high integration of semiconductor devices such as IC LSIs, interconnection technology between elements formed at high density, that is, multilayer interconnection technology becomes extremely important.

Most conventional LSIs have two or more wiring layers, but when the wiring structure is made into a multilayer structure, the steps of the interlayer insulating film and the conductive film for wiring accumulate, and the part of the step Each layer becomes thinner.

For this reason, disconnections in wiring layers and short circuits between wiring layers through interlayer insulating layers are likely to occur at step portions, and it is not necessarily suitable for multilayer wiring from the viewpoint of yield and reliability.

For this reason, as shown in a schematic cross-sectional view in FIG. 1, a coated glass film 2 is formed on the aluminum wiring layer 1, which is the lower wiring layer, by a spinner method or the like, and the aluminum wiring layer 10 is made to have a step height difference. An aluminum wiring layer 4 as an upper wiring layer is provided via a silicon oxide layer 3 as an interlayer insulating layer.

In the figure, 5 is a substrate such as a silicon wafer on which elements are formed, and 6 is an insulating film such as a silicon oxide film formed by thermally oxidizing the surface of this substrate.

However, even in the multilayer wiring obtained by this method, the difference in level of the lower wiring layer 10 is alleviated by the coated glass film 2, but the thickness of the coated glass film 2 is generally 500A.
Because of the following, the step coverage of the interlayer insulating film 3 and the upper wiring layer 4 cannot be eliminated, and the various problems in the multilayer wiring described above cannot be solved.

Therefore, an object of the present invention is to solve the various problems mentioned above, and to provide a highly reliable and high-yield manufacturing method for multilayer wiring, which eliminates step portions in multilayer wiring and prevents defective accidents associated therewith. be.

In order to achieve these objectives, the present invention includes a step of forming a conductive film on the entire surface of the substrate, and selectively removing the conductive film to form a pedestal for multilayer wiring at a predetermined distance from the lower wiring layer. This is a multilayer wiring manufacturing method consisting of the steps of: providing an insulator in the gap between the lower wiring layer and the multilayer wiring pedestal using a coating method; and providing an upper wiring layer via an interlayer insulating film. be.

DESCRIPTION OF THE PREFERRED EMBODIMENTS A method for manufacturing multilayer wiring in a semiconductor device according to an embodiment of the present invention will be described in detail below in order of steps with reference to the drawings.

(7) A starting material having a field insulating film 11 made of a silicon oxide film or the like on the surface of a silicon wafer 10 whose cross-sectional view is schematically shown in FIG. 2 is prepared.

The silicon wafer 11 has undergone various wafer treatments such as selective impurity diffusion, thermal oxidation, and photoetching, and is provided with elements such as diodes and transistors.

Note that various types of starting materials can be used, and desired multilayer wiring is provided on this starting material.

(a) A conductive film, for example, an aluminum layer 12, which will serve as a lower wiring, is formed on the entire surface of the field insulating film 11 by vacuum evaporation or the like to a thickness of about 1 μm (FIG. 3).

0) The aluminum layer 12 is selectively removed using photo-etching technology or the like to form an aluminum layer 12a which is a lower wiring pattern, and a pedestal for multilayer wiring is formed adjacent to this aluminum layer 12a for lower wiring. Aluminum layer 12b is formed at the same time (fourth
The aluminum layer 12b, which is a pedestal for multilayer wiring, is provided to eliminate as much as possible the step portion in the multilayer wiring. , are formed at the same time as the aluminum layer 12a, which is the lower layer wiring, and by making the distance between them as small as possible with a value that guarantees electrical insulation or more, it is easy to make their surfaces coincide with each other. be able to.

This separation distance is determined by the aluminum layer 12a, which is the lower layer wiring.
The thickness is selected in relation to the film thickness of the aluminum layer 12a, but it is set to 1 to 4 μm due to manufacturing technology limitations such as mask alignment accuracy in the current photo-etching of the aluminum layer 12a.

(d) The space between the lower wiring and the multilayer wiring pedestal is buried with an insulating material, and in order to flatten their surfaces, a coated glass film 13 is formed by applying glass mixed with a solvent using a spinner or the like (see Fig. 6). ).

This coated glass is first coated with each aluminum layer 12.
After entering the gap between the aluminum layers 12a and 12b and filling it, a thin film (approximately 0.5 μm thick) is applied to the surfaces of the aluminum layers 12a and 12b.

Therefore, the surface of this coated glass film 13? , it becomes flat as shown.

(9) A phosphosilicate glass (PSG) layer 14 as an interlayer insulating layer is formed on the entire surface of the coated glass film 13 to a thickness of about 0.6 μm by the CVD method.

Next, after providing the phosphosilicate glass layer 14Fc through-hole, an aluminum layer 18 for upper layer wiring is formed over the entire surface by vacuum deposition or the like (FIG. 7).

In the present invention, an aluminum layer 1 as a lower layer interconnection is used.
Even if the interlayer insulating layer 14 and the upper wiring layer 15 are provided on the layer 2a, the surfaces thereof can be made flat.

(To) Form the upper layer wiring pattern 15a by photo-etching technology (FIG. 8 shows its plan view, and FIG.
A sectional view taken along the BB' arrow in the figure is shown).

Since the surface of the phosphosilicate glass film 140, which is an interlayer insulating film, is flat, the aluminum layer 1 as an upper layer interconnection has a flat surface.
5a is not on the aluminum layer 12a as the lower layer wiring, the aluminum layer 15 as the upper layer wiring
As a result, no five-level difference occurs in a.

As mentioned above, the method for manufacturing multilayer wiring according to the present invention is that when forming the lower layer wiring pattern, a part of the aluminum layer, which was conventionally removed as unnecessary, is left in order to eliminate steps in the multilayer wiring. A pedestal for multilayer wiring is provided.

Then, the gap between the lower wiring and the pedestal is filled with a coated glass film, etc., and its surface is made flat as a base for providing an interlayer insulating layer. This is to prevent this from occurring.

Therefore, in the multilayer wiring obtained by the present invention, the interlayer insulating layer and the upper wiring layer do not become thinner or break even at the stepped portion of the lower wiring layer, and there is no disconnection in the wiring layer or breakage in the interlayer insulation layer. There are no defects such as short circuits between wiring layers, and highly reliable multilayer wiring can be obtained at a high yield.

Furthermore, according to the method for manufacturing multilayer wiring according to the present invention, since there are no stepped portions in the wiring layer and the interlayer insulating film, multilayer wiring can be obtained by microfabrication, which allows for high wiring density and highly integrated IC. Electronic components such as LSI can be obtained.

The present invention uses a conductive polycrystalline silicon layer or the like as a wiring layer.
The present invention can be applied to various methods of manufacturing multilayer wiring in which polyide resin or the like is appropriately used as the buried insulator.

[Brief explanation of the drawing]

Figure 1 is a cross-sectional view showing conventional multilayer wiring, Figures 2 to 9
The figures are plan views or cross-sectional views showing, in order of steps, a method for manufacturing multilayer wiring in a semiconductor device according to an embodiment of the present invention. ? ．． 12a... lower layer wiring, 2, 13...
・Coated glass film, 3, 14...Interlayer insulating film, 4
, 15a... upper layer wiring, 5, 10...
Silicon wafer 6, 11...field insulating film, 12...aluminum layer, 12b...
... Pedestal for multilayer wiring, 15 ... Aluminum layer

Claims (1)

[Claims] 1. A step of forming a conductive film on the entire surface of the substrate, a step of selectively removing the conductive film and providing a lower wiring layer and a multilayer wiring pedestal at a predetermined distance from the lower wiring layer, A method for producing multilayer wiring, which includes the steps of embedding an insulating material in the gap between the layer and the vedestal for multilayer wiring by a coating method, and providing an upper wiring layer via an interlayer insulating film. 2. The method for manufacturing a multilayer wiring according to claim 1, wherein the separation distance is several times or less the film thickness of the lower wiring layer. 3. The method for manufacturing multilayer wiring according to claim 1, in which coated glass is used as the buried insulator.