JPS5849B2 - Micro program data guide - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data processing device controlled by a microprogram, that is, a microprogram-controlled data processing device.

Microprograms handled by microprogram-controlled data processing devices include processing microprograms that require high processing speed and processing microprograms that do not require such high processing speed.

Taking a microprogram-controlled computer as an example, processing that requires high processing speed includes data transfer processing for input/output devices, execution processing of frequently used macro instructions, etc. Examples of unnecessary processing include startup and termination processing of low-speed input/output devices, execution processing of macro instructions that are used infrequently, console control processing, and the like.

When configuring a microprogram in a microprogram-controlled data processing device, if high processing speed is generally important, each microinstruction is constructed from microinstructions with a large number of bits in order to maximize the control information of parts that can be controlled simultaneously. If the emphasis is on cost reduction rather than processing speed, each microinstruction consists of a small number of bits so that the capacity of the microprogram storage device that accommodates the microprogram is small. A group of microinstructions is used.

However, conventional microprogram-controlled data processing devices require high processing speeds because they can only employ microprograms that are composed of one type of microinstruction group depending on the above-mentioned emphasis. Both processing that requires high processing speed and processing that does not require such high processing speed are executed using the same microinstruction group.

Therefore, if a microinstruction group with a large number of constituent bits is used, the capacity of the microprogram storage device will increase, while if a microinstruction group with a small number of constituent bits is adopted, the processing capacity will decrease. It has drawbacks such as:

Therefore, the main objects of the present invention are to provide a microprogram composed of a group of microinstructions with a large number of configuration bits suitable for increasing processing speed, and a structure suitable for reducing the capacity of a microprogram storage device. An improved microprogram-controlled data processing device that has high processing capacity and increases the efficiency of using a microprogram storage device by allowing microprograms consisting of a group of microinstructions with a small number of bits to coexist. Our goal is to provide the following.

According to the present invention, a first microprogram storage device that stores a microprogram constituted by a group of microinstructions each consisting of a fixed length microinstruction of one word unit; a second microprogram storage device that stores a microprogram constituted by a microinstruction couple group consisting of a microinstruction couple in units of 2 words that is a combination of two microinstructions capable of It includes a micro-sequence counter that stores the address of a micro-instruction in a micro-program storage device, and a micro-instruction register for two words. When a microinstruction is set, the execution of the microinstruction in units of 1 word is controlled, and when a microinstruction couple in units of 2 words of the microinstruction couple group is set in 2 words of the microinstruction register, a microprogram controller for controlling the execution of simultaneous operations of the microinstructions forming the microinstruction couple;
means for detecting information of a signal having information on which of the first microprogram storage devices the instruction is to be read; A one-word microinstruction read from the first microprogram storage device is set in each of two words of the microinstruction register, and the information detection means reads the instruction from the second microprogram storage device. a microinstruction retrieval control device that sets a microinstruction couple in units of 2 words read from the second microprogram storage device in 2 words of the microinstruction register when the microinstruction group is detected. A microprogram-controlled data processing device is obtained, which is characterized in that a microprogram constituted by the above microprogram and a microprogram constituted by the microinstruction couple group described above can coexist.

The first microprogram storage device and the second microprogram storage device described above may be separate storage devices or may be included in the same storage device, and the present invention does not specify these. do not have.

Moreover, as the above-mentioned information detection means, one having a configuration as shown below can be used.

(1) If the first microprogram storage device and the second microprogram storage device are consecutive in terms of addresses, a device configured to obtain a signal obtained by decoding the contents of the microsequence counter can be used.

(2) A flip-flop whose set and reset can be controlled by the above-mentioned microinstruction group and microinstruction couple group is used.

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

The microprogram-controlled data processing device of this embodiment runs a microprogram consisting of a microinstruction group (hereinafter referred to as the microinstruction group of cylinder 1) each consisting of a fixed-length microinstruction MI of one word. A microprogram storage device 1 to accommodate the microinstruction couple and a 2-word microinstruction couple (the first word is Mll and the second word is MI2), which is a combination of two of the above microinstructions that can operate simultaneously. A microprogram storage device 2 that stores a microprogram constituted by a group of microinstruction couples (hereinafter referred to as the microinstruction group of Box 2).
and a microinstruction retrieval control device 3 that performs control to set the microinstructions retrieved from the microprogram storage devices 1 and 2 into the microprogram control device 4.
When executing a microprogram composed of the instructions MI of the first microinstruction group, the execution of microinstructions in units of one word is controlled, but the instruction couple M11 and MI2 of the second microinstruction group controls the execution of microinstructions in units of one word. It comprises a microprogram controller 4 which controls the execution of simultaneous operations of the microinstructions forming each of the couples when executing the configured microprograms.

In the case of this embodiment, the microprogram storage devices 1 and 2 are included in the same storage device and are arranged consecutively in terms of addresses.

The microprogram control device 4 has microinstruction registers 41 and 42 and a microsequence counter 43 that stores the addresses of microinstructions stored in the microprogram storage devices 1 and 2 that are consecutive in terms of addresses.

The microinstruction retrieval control device 3 includes a selection circuit 31 that selects whether the microinstruction to be set in the microinstruction register 41 is MI or Mll according to a selection signal 34, and a selection circuit 31 that selects whether the microinstruction to be set in the microinstruction register 42 is MI or Mll.
or MI2 according to a selection signal 34.
2 and the address indicated by the microsequence counter 43, or the microprogram storage device 1.
, the selection circuits 31 and 32 both select MI, while the microprogram storage device 2
, the selection circuits 31 and 32 each select M11.
．． It is comprised of a selection signal generation circuit 33 that generates a selection signal 34 to select MI2.

If the microsequence counter 43 indicates the microprogram storage device 1, the selection signal generation circuit 33 detects this and sends both the selection circuits 31 and 32 an M
A selection signal 34 is generated to select I.

Microinstruction MI retrieved from microprogram storage device 1 is input to selection circuits 31 and 32.

The selection circuits 31 and 32 select the extracted microinstruction MI in response to the selection signal 34 and set it in the microinstruction registers 41 and 42.

The microprogram control device 4 executes the M11 instruction because the same microinstruction MI is set in the microinstruction registers 41 and 42.

On the other hand, if the microsequence counter 43 indicates the microprogram storage device 2, the selection signal generation circuit 3
3 detects this and generates a selection signal 34 to select circuits 31 and 32 to select MII and MI2, respectively.

The microinstructions MII and MI2 taken out from the microprogram storage device 2 are sent to the selection circuit 31 by Mll.
I2 is input to the selection circuit 32.

In response to the selection signal 34, the selection circuit 31 selects Mll and the selection circuit 32 selects MI2, respectively, and stores Mll in the microinstruction register 41 and MI2 in the microinstruction register 42.
Set.

The microprogram control device 4 executes the microinstruction M11 set in the microinstruction registers 41 and 42.
, MI2, each microinstruction M11 constituting the couple
゜MI2 is executed at the same time.

In this way, a microprogram consists of a first group of microinstructions consisting of microinstructions in units of one word, and a second group of microinstructions consists of a couple of microinstructions in units of two words. The microprograms executed coexist.

The detailed operation of how the microprogram control device 4 controls the execution of the first and second groups of microinstructions has been described by the present applicant in a publication entitled ``Microprogram Control Device 1''. Please refer to the specification of Japanese Patent Application No. 45681 (Japanese Unexamined Patent Publication No. 50-138747) filed in 1972, which has already been proposed.

As is clear from the above description, according to the present invention, there is provided a microprogram composed of a microinstruction couple group (second microinstruction group) having a large number of configuration bits suitable for increasing processing speed; A microprogram that has high processing ability and allows coexistence of a microprogram consisting of a microinstruction group (first microinstruction group) with a small number of configuration bits suitable for reducing the capacity of a storage device. An improved microprogram controlled data processing system is obtained which increases the efficiency of memory usage.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the main parts of an embodiment of the present invention. 1: A microprogram storage device that accommodates a microprogram constituted by a microinstruction group (first microinstruction group) consisting of microinstructions MI in one-word units;
2: Microinstruction couple in 2-word units M11. M.I.
2: a microprogram storage device accommodating a microprogram constituted by a microinstruction couple group (second microinstruction group); 3: a microinstruction retrieval control device; 31: a selection circuit for selecting M11/MI; 32: Selection circuit for selecting MI2/MI, 33:
a selection signal generation circuit that decodes the address of the microsequence counter and generates a selection signal; 34: a selection signal that prompts selection of the selection circuit; 4: microprogram control device; 41 and 42: microinstruction register; 43: Microsequence counter.

Claims (1)

[Claims] 1 a first microprogram storage device that stores a microprogram constituted by a group of microinstructions each consisting of a fixed-length microinstruction of one word; a second microprogram storage device for accommodating a microprogram constituted by a group of microinstruction couples each consisting of a two-word unit of microinstruction couples; in the first and second microprogram storage devices; It includes a micro-sequence counter accommodating the addresses of the micro-instructions, and a 2-word micro-instruction register, and the same 1-word micro-instructions of the micro-instruction group are set in each of the two words of the micro-instruction register. When the microinstruction couple of the microinstruction couple group is set in the second word of the microinstruction register, the microinstruction couple is executed. a microprogram control device for controlling the execution of simultaneous operations of the constituent microinstructions; means for detecting information of a signal having information on which of the first and second microprogram storage devices the instructions are to be read; When this information detecting means detects reading of an instruction from the first microprogram storage device, the microinstruction in units of one word read from the first microprogram storage device is transferred to two words of the microinstruction register. and when the information detecting means detects the reading of an instruction from the second microprogram storage device, it sets the microinstruction couple in units of 2 words read from the second microprogram storage device. It is equipped with a microinstruction retrieval control device that sets the two words of the microinstruction register, and enables coexistence of a microprogram made up of the above microinstruction group and a microprogram made up of the above microinstruction couple group. A microprogram-controlled data processing device characterized by: