JPS5850054B2 - PLL circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a PL that reproduces optimal identification timing from irregularly intermittent input signals, such as the NRZ or RZ system.
This relates to an L (Phase Locked Loop) circuit.

As shown in FIG. 1, the PLL circuit includes a phase comparator CMP.
, a low-pass filter LPF, and a voltage controlled oscillator ■CO.

Phase comparator CMP uses input clock 1 and voltage controlled oscillator ■
It detects the phase difference of the CO output clock 2 and converts it into a voltage.

The output 3 of the phase comparator CMP includes not only the frequency component of the phase difference but also a frequency component higher than the input signal.

The low-pass filter LPF integrates and smoothes the output voltage 3 of the phase comparator CMP, extracts only a continuous voltage component proportional to the phase difference, and also suppresses the phase difference component using its constant.

Voltage controlled oscillator ■CO is an oscillator whose oscillation frequency is controlled by the output voltage 4 of the low-pass filter LPF,
In a minute range, the oscillation frequency changes in proportion to the control voltage.

In PCM transmission, a received signal has phase fluctuations (jitter) due to various causes such as transmission path distortion, fluctuation, noise, and code amount interference.

It is desired that the identification timing clock follows gradual frequency fluctuations of the input and suppresses only these phase fluctuations (sick).

The role of the PLL circuit used for timing extraction is to reproduce an identified timing clock that satisfies these conditions.

Currently, ICs for PLL circuits including phase comparator CMP10, pass filter LPF, voltage controlled oscillator ■CO, etc. are commercially available, but non-return ICs used for PCM transmission
No phase comparator has been put to practical use that can function satisfactorily even for irregularly intermittent input signals such as a two-to-zero (NRZ) signal and a return-to-zero (RZ) signal.

FIG. 2 shows an example of a PLL circuit used for conventional timing extraction.

The block diagram in FIG. 2a is a PLL circuit for RZ input 5.

A recovered clock 1' synchronized with the input is supplied to the PLL circuit PLL by a clock continuation circuit C8C such as a tank circuit, and a jitter-free clock is recovered.

The block diagram in FIG. 2 shows a PLL circuit for the NRZ input 5'.

The NRZ input 5' generates rising and falling pulses by the differentiating circuit DIF, and the differentiating pulse 6 drives a clock continuation circuit C8C such as a tank circuit.
The reproduced clock 1' is supplied to the PLL circuit PLL, and a jitter-free clock is reproduced.

All of these circuits include circuits that make the clock continuous, and therefore include analog adjustment circuits such as tank circuits.

Therefore, in such conventional technology, it is necessary to adjust the tuning frequency of the tank circuit, and it is also essential to have a delay line, etc. to set the optimum discrimination time, and the adjustment of the optimum discrimination time is necessary depending on the bit rate. When the value becomes low, it becomes extremely difficult.

It also includes steady phase changes due to changes in element values due to aging and temperature changes.

For this reason, there is a drawback that requirements for the element become stricter in order to obtain the optimum identification timing.

The present invention eliminates these drawbacks! This method uses a voltage-controlled oscillator circuit using a crystal resonator, and uses the sum of the differential waveform of the mark signal of the input data and the output signal of the voltage-controlled oscillator as the clock of the toggle-operated phase comparator. This provides a PLL circuit constructed entirely of digital logic circuits without using a clock serialization circuit such as a tank circuit, thereby eliminating the need for analog adjustments and reducing the requirements for circuit elements. It is a relief.

This will be explained below according to the drawings.

FIG. 3 is a diagram showing an embodiment of the present invention, and includes a block diagram (a) showing a circuit for extracting the optimum identification timing from a data signal input transmitted in the NRZ system and a time chart thereof (a). b) in the same figure.

In the figure, DIF1 is a differentiation circuit that differentiates the input data 5 cut mark signal and outputs an output signal 7 having narrow pulses at the rising and falling parts, and is an inverter that delays the input signal. It consists of an exclusive OR circuit.

DIF2 is a differentiating circuit that differentiates the output clock 2 of the voltage controlled oscillator CO and outputs an output signal 8 having a narrow pulse at the rising edge. It is made up of circuits.

Also, AG is an AND gate, FF is a D-type flip-flop, OG is an OR gate, TPC is a toggle-operated phase comparator mainly composed of D-type flip-flops, FIL is a filter, and voltage controlled oscillator CO A voltage controlled oscillator using a crystal resonator is used.

A D-type flip-flop FF receives the output signal 8 of the differentiating circuit DEF2, and an AND gate A receives its output.
The output signal 7 of the differentiating circuit DIF1 is controlled by the signal G and the signal shown at 9 in FIG. 3 is generated and outputted from the AND gate AG.

That is, between each pulse of this signal 9, the voltage controlled oscillator ■
The number of pulses of signal 8, which is a differential waveform of the output pulse of CO, is always an odd number.

This signal 9 is converted by the OR gate OG into a signal 10 which is the sum of the signal 8 and sent to the toggle operation type phase comparator TPC.

Here, the flip-flop FF and the anime game-1-A
G prohibits the signals 8 and 9 from being input to the toggle operation type phase comparator TPC at the same time, thereby preventing abnormal operation in the operation uncertain region due to the differential pulse width.

The signal shown at 11 in FIG. 3 is the final phase comparator output of this circuit and is sent via filter FIL to voltage controlled oscillator VCO.

In this way, the signal 9 and the voltage controlled oscillator ■CO output clock 2 are controlled so that an odd number of differential pulses of the output clock 2 of the voltage controlled oscillator ■CO always enter between the differential pulses of the input data 5' of the NRZ. The sum of the differentiated signal 8 operates the toggle operation phase comparator TPC■, and the output of the phase comparator operates the PLL circuit.

If loop feedback is applied so that 0 or 1 continues, the differential pulse of the output clock 2 from the voltage controlled oscillator VCO will be supplied to the toggle operation phase comparator TPC, and a clock with a 50% duty ratio will be generated. Therefore, it operates equivalently as if no phase comparison is being performed.

As a result, the PL that reproduces the identification timing clock without causing phase synchronization even if O's or 1's are consecutively applied.
L circuit becomes possible.

Above, the extraction of the optimal identification timing from the data signal input transmitted by the NRZ method has been explained using the embodiment shown in FIG. explain.

FIG. 4 is a diagram showing an embodiment of the present invention, in which a block diagram showing its configuration is shown in FIG. 4, and a time chart for explaining its operation is shown in FIG. 4B.

In the figure, DIF3゜DBF4 is the mark signal of input data 5 or the output clock 2 of voltage controlled oscillator ■CO.
This is a differentiating circuit that differentiates the output signal 7 or 8' and outputs an output signal 7 or 8' having narrow pulses at the rising and falling parts, respectively, and is composed of an inverter that delays the input signal and an exclusive OR circuit. There is.

In addition, OG is an OR gate, TPC is a toggle operation phase comparator mainly composed of D-type flip-flops, and F
IL is a filter, and the voltage controlled oscillator CO uses a voltage controlled oscillation circuit using a crystal resonator.

The output signal 7 of the differentiating circuit DIF3 and the output signal 8 of the differentiating circuit 4 are converted into a sum signal 10' by the OR game 1-OG, and input to the toggle operation phase comparator TPC.

By doing this, the output signal 8 is the differential waveform of the output clock 2 of the voltage controlled oscillator VCO between each pulse of the output signal 7, which is the differential waveform of the mark signal of the input data 5.
′ is always an odd number of pulses.

In the O continuous period, a clock with a duty ratio of 50φ is generated by the differential pulse of the output clock 2 of the voltage controlled oscillator ■CO, and phase comparison is not equivalently performed, as in the case of the NRZ system.

In this embodiment, a clock phase inversion function is also provided in consideration of the case where the identification timing clock has a falling edge in the mark signal portion of the input data.

The block indicated by CPC in FIG. 4a is this phase control circuit, which is composed of an exclusive OR circuit, an inverter forming a differentiating circuit, an OR circuit, an OR circuit, a D type flip-flop, and the like.

The output clock 2 of the voltage controlled oscillator ■CO is supplied to the differentiating circuit via the exclusive OR circuit, and its falling portion is taken out as a negative differential pulse.

By applying an OR signal of this differential pulse and an inverted signal of the input data to the flip-flop, this flip-flop is set only when the falling edge of clock 2 comes to the mark signal portion of the input data.

When this flip-flop is set, the exclusive OR circuit inverts the phase of the output clock 2 of the voltage controlled oscillator VOC.

The clock controlled in this manner is sent out as an identification timing clock.

As explained in detail above, the PLL circuit of the present invention does not include any analog circuits such as a tank circuit or a delay line.
Since it is composed of only digital logic circuits, not only does the troublesome adjustment of analog circuits become unnecessary, but also the requirements for each circuit element can be relaxed.

[Brief explanation of the drawing]

FIG. 1 is a diagram for explaining the basic configuration of a PLL circuit, FIG. 2 is a block diagram for explaining a conventional PLL circuit for RZ or NRZ input, and FIG. 3 is for explaining an embodiment of the present invention. FIG. 4 is a block diagram and time chart for explaining another embodiment. DIFI~DIF4... Differential circuit, AG...
...and gate, OG...or gate, F
F...D type flip-flop, TPC.
...Toggle operation type phase comparator, ■CO...
・Voltage controlled oscillator, CPC...phase control circuit.

Claims (1)

[Claims] I In a PLL circuit for reproducing optimal identification timing from a data signal input transmitted using the NRZRZ method, a first pulse generating circuit that generates narrow pulses at the rising and falling edges of a mark signal of input data is used. and a second means for generating a narrow pulse at the rising or falling edge of the output clock from the voltage controlled oscillator, and the output pulse of the second means is always an odd number between the output pulses of the first means. and third means for controlling the output pulses of the first means so as to control the output pulses of the first means and supplying the sum of the output pulses of both means as a clock to a spike-operated phase comparator. . In a PLL circuit for reproducing optimal identification timing from a data signal input transmitted by the Z RZ method, a first means for generating narrow pulses at the rising and falling edges of a mark signal of input data, and a voltage a second means for generating narrow pulses at the rising and falling edges of the output clock from the controlled oscillator; and a third means for supplying the sum of the output pulses of both of these means to the toggle-operated phase comparator as its clock. A PLL circuit comprising: 3. The PLL circuit according to claim 2, further comprising fourth means for inverting the clock phase by detecting coincidence between the mark signal of the human input data and the falling edge of the clock.