JPS5850369B2 - Data transfer method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data transfer method for an information processing device, and particularly to a data transfer method from a temporary storage buffer to a variable-length storage memory.

Conventionally, there is a cycle steal method as a method for efficiently transferring data.

In the cycle steal method, if a memory area (hereinafter referred to as a storage area) in which data is to be stored is specified in advance, data transfer is performed without program intervention until the following conditions are met.

The conditions are when there is no more storage space in the designated storage area (hereinafter referred to as the number of remaining transfer bytes) and when a break in transfer data is detected.

Transfer data can be separated by specifying the number of bytes to transfer,
Alternatively, a method of specifying by writing a byte indicating a delimiter in the transfer data is usually used.

The latter method is used when the number of data to be transferred is unknown at the start of cycle stealing, such as when cycle stealing is performed by dividing each message in a line control device.

In any of the above methods, when reading m bytes of data from the buffer at a time and transferring it to the storage area, if the remaining number of transfer bytes in the storage area is equal to m bytes, this cycle steal is performed. When the process is completed, an interrupt (1) for the next storage area request is generated.

At this interrupt 11, the program needs to prepare the next storage area.

Since the delimiter instruction byte 3 is detected when data is read from the buffer, as shown in Figure 1, if there is no more transfer data, that is, the delimiter instruction byte 3 is written in the next byte. If so, a cycle steal completion interrupt 2 is generated when data is read in the next cycle steal operation.

In this case, not only will the storage area secured by the interrupt (1) that occurred earlier become useless, but the interrupt will occur twice in a short period of time, which will have an adverse effect on processing performance.

An object of the present invention is to provide a cycle steal method that suppresses the above-mentioned unnecessary interrupts and prevents a decrease in program processing performance.

A feature of the present invention is that in a method of reading data every m bytes from the buffer and transferring it to the storage area, the number of cycle steal transfer bytes is set to m1 byte only when the remaining number of transfer bytes is m bytes. This is to prevent new storage area requests from being interrupted.

This will be explained using FIG.

Consider a case where the number of transferred data becomes equal to the number of remaining transfer bytes in the k-th read, and in addition, byte 3 indicating a break is written in the first byte of the data to be read next.

As described above, in this case, if all the transfer data is transferred to the storage area, the storage area will be secured unnecessarily and the processing capacity will be reduced.

In the present invention, in the kth cycle steal operation, one byte immediately before the delimiter instruction byte 3 is left and transferred,
By transferring that 1 byte to the next +1st cycle steal operation, an interrupt will not occur at the kth time, and the number of remaining transfer bytes will be O and the cycle steal operation will be completed at the k+1st operation. Detect simultaneously and generate an interrupt.

By doing this, since the completion of the cycle operation at the time of an interrupt is detected, there is no need to further secure a storage area, and the number of interrupts can be reduced to one.

Next, one embodiment of the present invention will be described with reference to the drawings.

FIG. 3 shows a cycle steal type line control device showing one embodiment of the present invention.

To maintain generality, in this example, the number m of cycle steal bytes is assumed to be 2 bytes.

In this device, data from the line is assembled into bytes by a serial/parallel converter 4, and data 101, 102, 103 are stored in a buffer 1.
, 104.

On the other hand, the cycle steal control unit 5 has 101.102,
Data is transferred in the order of 103 and 104.

The all-serial/parallel converter 4 receives the data 101, 102, 103, and 104, and when the message ends, writes a height 105 after 104 indicating the message delimiter.

Assume that the cycle steal state is such that at the time of transferring 101 and 102, there are 2 bytes of free space in the storage area.

The byte 105 indicating the delimitation of the message is used to separate it from other data. For example, if the general data is 8 bits/byte, 9 bits/byte may be allocated for the byte 105 indicating the delimitation.

At this time, the number of remaining transfer bytes is 2, which matches the number of bytes that can be read at one time (2), so the number of cycle steal transfer bytes is reduced by 1 to 1.

That is, only 103 of the read data are stored in the read register 6.

At this point, the number of remaining transfer bytes is 1, and no interrupt occurs.

In the next cycle steal operation, 104 and 105 are read, but since 105 is a delimiter instruction byte, there is no need to store it in the memory, and only 104 is stored as one byte as the remaining transfer byte.

At this point, the number of remaining transfer bytes becomes 0 and an interrupt occurs, but since the end of the message is detected by the delimiter instruction byte 105, message end processing is started and unnecessary buffer reservation can be avoided.

Note that the present invention is applicable not only to the cycle steal method, but also to
Data transfer methods that do not require intervention from the program execution unit, such as DMA (Direct Memory Ac
It can also be easily applied to the cess) method.

As described above, according to the present invention, when there is no data to be transferred, no interrupt for the next buffer reservation request is generated, so that the processing performance of the program is not reduced.

[Brief explanation of drawings]

Figure 1a is a block diagram for explaining the conventional cycle steal method.
A time chart showing the relationship between steal operations and program processing, FIG. 2 is a block diagram for explaining the cycle steal method of the present invention, and FIG. 3 is a block diagram of a line control device showing an embodiment of the present invention. It is. 1...Buffer area, 2...Data byte, 3...Separator instruction byte, 4...
...Serial-to-parallel converter, 5...Cycle steal control unit, 6...Read register, 7...
...Memory, 8...Storage area, 9...
...Program execution section, 10...Interrupt, 1
1...Line data.

Claims (1)

[Claims] 1. A buffer that temporarily stores the data to be transferred and in which a delimiter instruction byte is written at the message end position;
a variable-length storage memory consisting of a plurality of fixed-length areas for storing data in the buffer, each of which is configured to be secured and connectable as desired; and a variable-length storage memory configured to read data in the buffer memory in transfer unit bytes. a control means for sequentially transferring the data to the storage memory, and when one fixed length area becomes full, securing the next fixed length area and performing data transfer until a message end instruction byte is read into the buffer. In the method, the control means increases the number of transferred bytes by 1 only when the untransferred data in the buffer reaches the number of transfer unit bytes for each data transfer.
A data transfer method characterized in that the data transfer method is configured to perform transfer after reducing the data.