JPS5850413B2 - Manufacturing method of semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of reducing thermal strain caused to a semiconductor slice during an impurity diffusion process.

For example, it is important for NPN transistors for high power and high voltage use to have a wide safe operating area (ASO) and high voltage characteristics. Special care is taken to form a diffusion layer.

A conventional manufacturing method will be explained below with reference to FIG.

To manufacture it, first, an N-type silicon slice 1
By applying a long-term diffusion treatment to the material, aluminum is diffused from both the front and back surfaces, and P with a long diffusion length is
After forming the type diffusion layers 2 and 3, the P-type diffusion layer 3 on one side (back side) is removed by mechanical or chemical polishing, and the collector layer 1 and base layer 2 are formed as shown in Figure 1a. Obtain a semiconductor slice.

Next, as already shown in FIG. 1, a silicon oxide film 4 is formed on the front surface side of the semiconductor slice to serve as a mask during emitter diffusion, and an emitter diffusion window 5 is further formed in this silicon oxide film.

Of these, an N-type impurity such as phosphorus is diffused through the window 5 to form an N-type emitter region 6 as shown in FIG. 1C.

In this step, phosphorus is also diffused throughout the back surface side of the semiconductor slice, and at the same time, a low resistivity collector layer I is formed.

Individual transistors are formed by dividing the semiconductor slice into which transistors have been formed through the above process by mesa etching.

In such conventional manufacturing methods, a diffusion layer 3 having a diffusion length equivalent to that of the base layer 2 is created when forming the base layer 2, and a mechanical or chemical polishing process is essential to remove this diffusion layer. becomes.

This polishing process may cause distortion, damage, or contamination of the silicon slice.

Furthermore, it is necessary to select the thickness of the silicon slice serving as the starting material, taking into consideration the thickness to be removed in the polishing step, which is disadvantageous in that it causes unnecessary loss of material.

In order to eliminate these drawbacks, a film such as a silicon oxide film that has a masking effect against impurities is formed in advance over one side of the silicon slice, and the side that is not covered by this film is Attempts have also been made to form a diffusion layer with a long diffusion length by diffusing impurities.

However, when performing a long-term diffusion treatment, it is necessary to make the above-mentioned film thicker.

Figure 2 shows the film thickness (to It is a figure which shows the relationship of length xj, in which a shows the relationship when the impurity is phosphorus, and b shows the relationship when the impurity is aluminum.

As shown in the figure, when the impurity is aluminum, the film is 1
．． If the film thickness is 5 μm or less, or 1.2 μm or less in the case of phosphorus, impurities will diffuse into the silicon slice, and the masking effect of the silicon dioxide film will be lost.

Therefore, the film that serves as a mask during the impurity diffusion process over a long period of time becomes very thick.

However, when a thick film is formed on the metal region of one side of a silicon slice and heat treated at high temperature for a long time, a large stress is generated due to the difference in thermal expansion between the two, resulting in cracks in the film and crystal distortion on the surface of the silicon slice. arise.

For this reason, such a method has not yet been put into practical use.

The present invention is a method for manufacturing a semiconductor device that eliminates all the disadvantages of the methods described above, reduces strain caused to semiconductor slices by thermal diffusion, and further eliminates damage and contamination of semiconductor slices. The feature of the present invention is that when impurities are diffused into a silicon slice from one side, a dividing line of the silicon slice is used as a mask to prevent the diffusion of impurities over the entire area of the other side. A film is formed from which a portion corresponding to the surface is removed, and impurities are diffused from the one surface side.

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 3a=d is a diagram showing the manufacturing process of a high voltage power transistor according to the method of the present invention.

In the method of the present invention, first, as shown in FIG. 3a, silicon dioxide films 4.4' having a thickness of 1.5 μm are formed on both sides of the N-type silicon slice 1 to serve as a mask during base diffusion.

Next, as already shown in FIG. 3, a photoresist 8 is coated on the silicon dioxide film 4 on the back side, leaving a portion corresponding to the dividing line 9 of the silicon slice.

When the silicon dioxide film is etched using this photoresist 8 as a mask, the silicon dioxide film 4 on the front side is completely removed, while the silicon dioxide film 4' on the back side is selectively removed.

Therefore, by going through this etching process, the third
As shown in FIG. C, a silicon slice is obtained in which the silicon dioxide film 4' is present only on the back side, and a portion 9' corresponding to the dividing line of the silicon slice has been removed.

Thereafter, aluminum is diffused in a furnace at 1200° C. for about 10 hours, thereby forming P-type diffusion layers 10 and 11 with a depth of about 30 μm, as shown in FIG. 3d.

The P-type diffusion layer 10 formed through the above process becomes the base layer of the transistor.

After removing all the silicon dioxide film on the back side,
An N-type impurity, such as phosphorus, is diffused from the surface side using well-known selective diffusion to form an N-type emitter region.

In this step, phosphorus is diffused all over the back side of the semiconductor slice, and at the same time a high concentration, low resistivity collector layer is formed.

Individual NPN transistors are formed by dividing the semiconductor slice in which transistors have been formed in this manner.

FIG. 4 is a diagram comparing and showing variations in breakdown voltage VOBO in the C-B direction of NPN type high breakdown voltage power transistors formed by the manufacturing method of the present invention and the conventional manufacturing method described above, and is illustrated in FIG. As can be seen, there is no difference in the reverse breakdown voltage of a transistor manufactured by the manufacturing method of the present invention and that of a transistor formed by the conventional manufacturing method, but the variation is due to the manufacturing method of the present invention. The number of cases due to methods is significantly lower.

This difference is due to the fact that in the manufacturing method of the present invention, a silicon oxide film removal section is provided, so even though the film thickness is reduced, thermal stress due to the difference in thermal expansion coefficient between silicon and silicon oxide film that occurs during the diffusion process is reduced. This is brought about by the fact that the silicon slice becomes smaller and almost no distortion or cracks occur in the silicon slice.

Note that impurities diffuse through this silicon oxide film removed part and a diffusion layer is formed, but this part corresponds to the dividing line of the silicon slice and is inevitably removed when dividing into individual elements. , there is no inconvenience.

As mentioned above, the manufacturing method of the present invention does not require polishing of silicon slices, and does not cause problems such as contamination, scratches, damage, or distortion due to polishing. Since the stress is reduced, there is no distortion or cracking due to thermal stress, and the manufacturing yield is greatly improved.

[Brief explanation of drawings]

Figure 1 a ''-c is a process diagram showing a conventional method for manufacturing a semiconductor device, Figure 2 is a diagram showing the relationship between the thickness of an oxide film and the depth of impurity diffusion into a semiconductor slice, and Figure 3 a '' d is a process diagram showing a method for manufacturing a semiconductor device according to an embodiment of the present invention, and FIG. 4 is a comparison diagram of the reverse breakdown voltage of an element formed by the method of the present invention and that by a conventional method. 1... N-type collector layer, 2, 10...
P-type base layer, 4,4... silicon dioxide film,
6...Emitsuku area, 8...Lugist,
9, 9'... Window corresponding to the dividing line of the silicon slice, 10, 11... P-type diffusion layer.

Claims (1)

[Claims] 1. When diffusing impurities into a silicon slice from one side of the silicon slice, a coating is formed by removing a portion corresponding to the dividing line of the silicon slice as a coating to prevent the diffusion of impurities over the entire area of the other side, A method for manufacturing a semiconductor device, characterized in that impurities are diffused from the one surface side.