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JPS5850424B2 - How to divide a semiconductor substrate - Google Patents
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JPS5850424B2 - How to divide a semiconductor substrate - Google Patents

How to divide a semiconductor substrate

Info

Publication number
JPS5850424B2
JPS5850424B2 JP54055989A JP5598979A JPS5850424B2 JP S5850424 B2 JPS5850424 B2 JP S5850424B2 JP 54055989 A JP54055989 A JP 54055989A JP 5598979 A JP5598979 A JP 5598979A JP S5850424 B2 JPS5850424 B2 JP S5850424B2
Authority
JP
Japan
Prior art keywords
diffusion
region
semiconductor substrate
dividing
channel stopper
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP54055989A
Other languages
Japanese (ja)
Other versions
JPS55148439A (en
Inventor
寛 三池
宏二 竹本
健一 立野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP54055989A priority Critical patent/JPS5850424B2/en
Publication of JPS55148439A publication Critical patent/JPS55148439A/en
Publication of JPS5850424B2 publication Critical patent/JPS5850424B2/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P54/00Cutting or separating of wafers, substrates or parts of devices

Landscapes

  • Dicing (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Description

【発明の詳細な説明】 本発明は複数個の半導体素子が作り込まれた半導体基板
を分割して個々に独立した半導体素子基板を得るための
半導体基板の分割方法に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor substrate dividing method for dividing a semiconductor substrate on which a plurality of semiconductor elements are fabricated to obtain individual semiconductor element substrates.

シリコン半導体素子基板は、通常、多数個の半導体素子
が作り込まれたシリコン基板を分割することによって得
られるが、作り込まれるシリコン半導体素子基板の面積
が定まっている場合、作り込むシリコン半導体素子数を
増し、シリコン基板の利用率を高めるためには個々の素
子間隔を極力狭くする配慮が払われる。
A silicon semiconductor element substrate is usually obtained by dividing a silicon substrate on which a large number of semiconductor elements are fabricated, but if the area of the silicon semiconductor element substrate to be fabricated is fixed, the number of silicon semiconductor elements to be fabricated is In order to increase the silicon substrate utilization rate, consideration is given to making the distance between individual elements as narrow as possible.

ところで、シリコン半導体素子基板の分割には、通常ダ
イヤモンドポイントによるスクライビング法等が用いら
れるが、これらはいずれもシリコン基板にある巾を持つ
歪層を形成する方法であり、上記のように素子間隔を狭
くする配慮を払った場合には、分割位置にわずかなずれ
が生じても個々の素子に悪影響が与えられ分断されたシ
リコン半導体素子の特性が損われるおそれがあった。
Incidentally, a scribing method using a diamond point is usually used to divide a silicon semiconductor element substrate, but these methods form a strained layer with a certain width on the silicon substrate, and as described above, the element spacing can be reduced. If consideration is given to making the area narrower, even a slight shift in the dividing position may have an adverse effect on the individual elements, and the characteristics of the divided silicon semiconductor elements may be impaired.

たとえば、プレーナ形トランジスタにおいては、チャン
ネルストッパ領域を分割ラインを含む幅広な領域として
作り込みこのチャンネルストッパ領域上に形成された酸
化膜を除去することによって形成した開孔部を目印とし
て分断がなされる。
For example, in a planar transistor, the channel stopper region is created as a wide region including a dividing line, and the oxide film formed on the channel stopper region is removed, and the division is performed using the opening formed as a mark. .

すなわち、光学顕微鏡を用いて開孔部の中心(チャンネ
ルストッパの領域の一中心)を目測する方法が一般に採
られているが正しい分割位置の割り出しが難しく、正し
い分割位置からのズレが生じ易い。
That is, a method is generally adopted in which the center of the opening (one center of the channel stopper area) is visually measured using an optical microscope, but it is difficult to determine the correct dividing position, and deviations from the correct dividing position are likely to occur.

すなわちチャンネルストッパ領域は通常数+μm以上の
巾を有し、この中心にダイヤモンドポイントを丁度位置
させることはきわめて困難である。
That is, the channel stopper region usually has a width of several plus micrometers or more, and it is extremely difficult to position the diamond point exactly in the center of the channel stopper region.

本発明は上記欠点に鑑みてなされたもので二酸化シリコ
ン膜(以下S i02膜と称す)等の絶縁膜をマスクと
して用いた選択拡散処理でシリコン基板内へ複数個の素
子を作り込むとともに、前記シリコン基板の分割ライン
に相当する微細領域部分の両側に上記の選択拡散処理を
利用して対向する拡散領域を作り込み、次いで対向する
拡散領域上ならびにこの間にある微細領域部分上のS
i02膜を選択的に除去し、このときに拡散部と非拡散
部のシリコン基板面との間に形成される段差を目印にし
、シリコン基板の分断を行うことにより、分割位置の選
定精度を高め、信頼性の高いシリコン素子基板を得よう
とするものである。
The present invention has been made in view of the above-mentioned drawbacks, and includes manufacturing a plurality of elements in a silicon substrate by selective diffusion treatment using an insulating film such as a silicon dioxide film (hereinafter referred to as Si02 film) as a mask, and Opposing diffusion regions are created on both sides of the micro region corresponding to the dividing line of the silicon substrate using the above selective diffusion process, and then S is formed on the opposing diffusion regions and on the micro region in between.
By selectively removing the i02 film and dividing the silicon substrate using the step formed between the silicon substrate surface of the diffused part and the non-diffused part as a mark, the selection accuracy of the dividing position is increased. , which attempts to obtain a highly reliable silicon element substrate.

次に、本発明実施例のプレーナ型トランジスタの形成さ
れた半導体基板の分割方法について図面を参照しつつ説
明する。
Next, a method for dividing a semiconductor substrate on which planar transistors are formed according to an embodiment of the present invention will be described with reference to the drawings.

第1図で示すようにn型シリコン基板1の中へ多数のp
型ベース領域2を作り込んだのち、ベース領域上を覆う
SiO2膜3にエミッタ拡散用の窓4を形成するフォト
エツチング処理を利用して、ベース領域間に位置するシ
リコン基板上部分を覆うS io 2膜3にチャンネル
ストッパ領域形成用の窓5および6を形成する。
As shown in FIG.
After forming the mold base region 2, a photo-etching process is used to form a window 4 for emitter diffusion in the SiO2 film 3 covering the base region, and an Sio film covering the upper portion of the silicon substrate located between the base regions is formed. Windows 5 and 6 for forming channel stopper regions are formed in the two films 3.

この窓5および6の形成にあたっては両者の間に残すS
iO2膜部分7が分割ライン上に位置し、しかもその幅
がダイヤモンド針の幅とほぼ等しい幅たとえば約35μ
m程度となるよう配慮する。
When forming these windows 5 and 6, S is left between them.
The iO2 film portion 7 is located on the dividing line, and its width is approximately equal to the width of the diamond needle, for example, approximately 35μ.
Care should be taken to ensure that the distance is around m.

次いで、n型不純物たとえば燐を拡散することにより第
2図で示すように、多数個のベース領域2の中へそれぞ
れn+型エミッタ領域8を形成する。
Next, as shown in FIG. 2, n+ type emitter regions 8 are formed in each of the plurality of base regions 2 by diffusing an n type impurity such as phosphorus.

この拡散処理時に窓5および6を通して燐が拡散し、n
+型チャンネルストッパ領域9,10および11が同時
に形成され、これらの領域間すなわちSiO2膜7の下
にはS io 2膜部分7の幅よりも狭い非拡散領域1
2も形成される。
During this diffusion process, phosphorus is diffused through windows 5 and 6, and n
+ type channel stopper regions 9, 10, and 11 are formed at the same time, and between these regions, that is, under the SiO2 film 7, there is a non-diffusion region 1 narrower than the width of the Sio2 film portion 7.
2 is also formed.

またこのとき領域9,10.11上に薄いSiO2膜1
3゜14.15が形成される。
Also, at this time, a thin SiO2 film 1 is formed on the regions 9, 10, and 11.
3°14.15 is formed.

こののち、電極形成用の窓あけとチャンネルストッパ領
域9,10および11の上と非拡散領域12の上に形成
されているSiO2膜13,14゜15.7の除去のた
めのエツチング処理を施す。
After this, an etching process is performed to open a window for electrode formation and to remove the SiO2 films 13, 14°15.7 formed on the channel stopper regions 9, 10, and 11 and on the non-diffusion region 12. .

第3図は上記の処理を経てSiO2膜7,13゜14.
15の除去がなされたチャンネルストッパ領域部分近傍
を拡大して示した断面図であり、エミツク拡散処理工程
での熱酸化によりチャンネルストッパ領域部分9,10
.11の上には新たにシリコン基板の酸化により形成さ
れた8102膜13.14,15が形成され、この新た
なSiO2膜13,14.15が除去されることにより
、チャンネルストッパ領域9,10.11の上面と非拡
散部分12の上面との間には段差が形成される。
FIG. 3 shows SiO2 films 7, 13°, 14. after the above treatment.
15 is an enlarged cross-sectional view showing the vicinity of the channel stopper region portion from which the channel stopper region portions 9 and 10 have been removed due to thermal oxidation in the emitter diffusion process.
.. New 8102 films 13, 14, 15 formed by oxidizing the silicon substrate are formed on top of 11, and by removing these new SiO2 films 13, 14, 15, channel stopper regions 9, 10, . A step is formed between the upper surface of the non-diffusion portion 11 and the upper surface of the non-diffusion portion 12 .

この段差は、光学顕微鏡下で十分に識別することが可能
であり、第3図で示すように段差によって非拡散領域部
分12すなわち分割ラインを識別し、この部分にたとえ
ばダイヤモンド針13をセットし、こののちスクライブ
を施し、さらに押圧力を加えることにより、極めて正確
な分割が行われる。
This step can be sufficiently identified under an optical microscope, and as shown in FIG. 3, the non-diffusion region portion 12, that is, the dividing line, is identified by the step, and a diamond needle 13, for example, is set in this portion. After this, scribing is performed and further pressing force is applied to achieve extremely accurate division.

すなわち、第3図では段差がチャンネルストッパ領域9
,10の間に形成されており、この部分へのダイヤモン
ド針13のセットは容易で正確なスクライブを行うこと
ができる。
That is, in FIG. 3, the step is the channel stopper area 9.
, 10, and the diamond needle 13 can be easily and accurately set in this portion.

なお、チャンネルストッパ領域9,10の合計の巾は数
+μm程度でよいがその間の間隔は分断刃の幅に相当す
る程度に小さいのが望ましい。
The total width of the channel stopper regions 9 and 10 may be approximately several micrometers, but it is desirable that the interval therebetween be as small as the width of the dividing blade.

この方法では、側ら工数が増えることなく、拡散用のマ
スク変更のみで、チャンネルストッパー領域形成と同時
に、微少幅の分割ライン形成がなされるところとなり、
この分割ラインを目印として、容易に精度良い分割を行
うことが可能である。
With this method, the minute width dividing line can be formed at the same time as the channel stopper region is formed by simply changing the mask for diffusion without increasing the number of man-hours.
Using this dividing line as a mark, it is possible to easily perform accurate division.

またここでは、トランジスタについてのみ述べたが、ダ
イオードについても同様であり、さらに必ずしも段差の
形成は、エミッタ領域形成の為の拡散処理を利用する必
要はなく、たとえば、ベース拡散処理あるいは独立した
拡散処理によって行ってもよい。
Although only transistors have been described here, the same applies to diodes, and the formation of steps does not necessarily require the use of a diffusion process for forming an emitter region; for example, a base diffusion process or an independent diffusion process. You can also do this by

以上説明してきたように、本発明の方法は拡散処理によ
って基板表面上に形成された酸化シリコン膜等の絶縁膜
を除去したのちに、非拡散領域と拡散領域の間に生じる
段差を利用して微少中の分割ラインを形成しておき、こ
れを光学的に認識することによりここに、分断刃をあて
て分割を行うものであり、非常に精度の良い分割を行う
ことが可能である。
As explained above, the method of the present invention removes an insulating film such as a silicon oxide film formed on the substrate surface by diffusion treatment, and then utilizes the step difference between the non-diffused region and the diffused region. By forming a minute dividing line and optically recognizing it, the dividing blade is applied to the line to perform the division, and it is possible to perform extremely accurate division.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明実施例の方法で分割を行う際、エミッタ
領域およびチャンネルストッパー領域形成用の拡散マス
クを形成した状態を示すシリコン基板の断面図、第2図
は同拡散後の状態を示す断面図、第3図は同酸化膜除去
後のチャンネルストッパー領域部分の拡大断面図である
。 1・・・・・・n型シリコン基板、2・・・・・・p型
ベース領域、3・・・・・・酸化シリコン膜、4・・・
・・・エミッタ拡散用窓、5,6・・・・・・チャンネ
ルストッパ形成用窓、7・・・・・・酸化シリコン膜部
分、8・・・・・・n+型エミッタ領域、9,10,1
1・・・・・・チャンネルストッパ領域、12・・・・
・・非拡散領域、13・・・・・・ダイヤモンド針。
FIG. 1 is a cross-sectional view of a silicon substrate showing a state in which a diffusion mask for forming an emitter region and a channel stopper region is formed when dividing by the method of the embodiment of the present invention, and FIG. 2 shows the state after the same diffusion. 3 is an enlarged sectional view of the channel stopper region after the oxide film is removed. 1... N-type silicon substrate, 2... P-type base region, 3... Silicon oxide film, 4...
...Emitter diffusion window, 5, 6...Channel stopper formation window, 7...Silicon oxide film portion, 8...N+ type emitter region, 9, 10 ,1
1... Channel stopper area, 12...
...Non-diffusion region, 13...Diamond needle.

Claims (1)

【特許請求の範囲】[Claims] 1 半導体基板内へ絶縁膜をマスクとする選択拡散で複
数個の素子を作り込むとともに前記半導体基板の分割ラ
インに相当する領域部分の両側に、上記の選択拡散又は
これとは別の選択拡散で対向する2個の拡散領域を離間
して作り込み、次いで前記対向する拡散領域上ならびに
この間にある微細領域部分上の絶縁膜を選択的に除去し
、このときにできる拡散部と非拡散部の前記半導体基板
表面の段差を目印にし、前記基板の分断を行うことを特
徴とする半導体基板の分割方法。
1. A plurality of elements are fabricated into a semiconductor substrate by selective diffusion using an insulating film as a mask, and the above-mentioned selective diffusion or another selective diffusion is applied to both sides of the region corresponding to the dividing line of the semiconductor substrate. Two opposing diffusion regions are created with a distance between them, and then the insulating film on the opposing diffusion regions and on the fine region between them is selectively removed, and the resulting diffusion and non-diffusion regions are separated. A method for dividing a semiconductor substrate, characterized in that the substrate is divided using a step on the surface of the semiconductor substrate as a mark.
JP54055989A 1979-05-08 1979-05-08 How to divide a semiconductor substrate Expired JPS5850424B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP54055989A JPS5850424B2 (en) 1979-05-08 1979-05-08 How to divide a semiconductor substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP54055989A JPS5850424B2 (en) 1979-05-08 1979-05-08 How to divide a semiconductor substrate

Publications (2)

Publication Number Publication Date
JPS55148439A JPS55148439A (en) 1980-11-19
JPS5850424B2 true JPS5850424B2 (en) 1983-11-10

Family

ID=13014490

Family Applications (1)

Application Number Title Priority Date Filing Date
JP54055989A Expired JPS5850424B2 (en) 1979-05-08 1979-05-08 How to divide a semiconductor substrate

Country Status (1)

Country Link
JP (1) JPS5850424B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4941897B2 (en) * 2008-02-06 2012-05-30 株式会社北村製作所 Cargo box rack structure of luggage collection and delivery vehicle

Also Published As

Publication number Publication date
JPS55148439A (en) 1980-11-19

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