JPS5850434B2 - Method for manufacturing field effect transistors - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a field effect transistor, and more particularly to a structure in which a gate electrode is formed on the bottom surface of a recess provided in the main surface of a semiconductor substrate (hereinafter referred to as a "recess structure"). The present invention relates to an improvement in a method for manufacturing a field effect transistor (called a field effect transistor).

Hereinafter, gallium arsenide (GaAs) metal semiconductor (Metal Sem1conductor: M
ES) This will be explained by taking a field effect transistor (FET') as an example.

Figure 1 shows a typical non-recessed GaAsMES FE.
It is a sectional view showing the structure of T.

In the figure, 1 is a semi-insulating ■-shaped GaAs substrate, and 2 is an N-type, P-type, or ■-type GaAs substrate epitaxially grown on the whole surface of the GaAs substrate 1 with an impurity concentration of 10''/c. The buffer layer 3 is epitaxially grown on the buffer layer 2 and has an impurity concentration of 1017/cf.
It is an M-type active layer with a size of about 1.

4 and 5 are source electrodes and drain electrodes formed on the active layer 3 at a predetermined distance from each other; 6 is a source electrode and a drain electrode formed on the active layer 3 between the source electrode 4 and the drain electrode 5; These are gate electrodes formed at a predetermined distance from each other.

Note that the active layer 3 between the source electrode 4 and the drain electrode 5
is the channel area.

The GaAs MES FET configured in this manner is used by applying a positive voltage with respect to the source electrode 4 to the drain electrode 5 and applying a negative voltage with respect to the source electrode 4 to the gate electrode 6.

In order to achieve high output of this GaAs MESFET, the current flowing between the source and drain (drain current) is
and the voltage applied between the source and drain (
Drain voltage) should be increased.

However, the drain current that can be controlled by reverse biasing the gate electrode 6 has the following limitations.

That is, if the impurity concentration of the active layer 3 is increased or its thickness is increased to increase the drain current,
It becomes difficult to pinch off the drain current due to the reverse bias of the gate electrode 6, and it becomes impossible to completely control the drain current.

Therefore, in order to achieve high output of the GaAsMES FET, it is necessary to increase the drain voltage applied between the source and drain.

When this drain voltage is increased, a voltage corresponding to the sum of the absolute values of the reverse bias voltage to the gate electrode 6 and the drain voltage is applied between the gate and the drain.

This gate-drain voltage increases electric field concentration at the end of the drain electrode 5 on the gate electrode 6 side, and the reverse breakdown voltage of the gate electrode 6 decreases.

Relieving electric field concentration at the end of this drain electrode 5,
In order to increase the reverse breakdown voltage of the gate electrode 6, it is known that a recess structure in which a recess is provided in a part of the surface of the active layer 3 in the channel region and the gate electrode 6 is formed within this recess is effective. There is.

FIG. 2 is a cross-sectional view showing the structure of a GaAs MES FET with a recessed structure.

In the figure, 7 is a recess provided in a part of the surface of the active layer 3 in the channel region, and 6a is a gate electrode formed on the bottom surface of the recess 7.

In this recessed GaAs MES FET, since the gate electrode 6a is formed in the recess 7, the electric field concentration at the end of the drain electrode 5 described above is alleviated, and the reverse breakdown voltage of the gate electrode 6a can be increased. can.

・Next, GaAs MES FET with conventional recessed structure
Each manufacturing step of the manufacturing method will be explained with reference to cross-sectional views shown in FIGS. 3A to 3C.

First, a buffer layer 2 and an active layer 3 are epitaxially grown on the entire surface of a GaAs substrate 1 in sequence.

Next, a source electrode 4 and a drain electrode 5 are formed on the active layer 3 by a well-known method [FIG. 3a].

Next, a photoresist film 8 is formed on the source electrode 4 and drain electrode 5, including the exposed surface of the active layer 3.

Next, the photoresist film 8 on the surface of the active layer 3 where the recess 7 shown in FIG. 2 is to be formed is removed by photolithography to form a hole 9 (FIG. 3b).

Next, using the photoresist film 8 in which the holes 9 are formed as a mask, a part of the surface of the active layer 3 is removed by etching to remove the recesses 7.
[Figure 3C].

Thereafter, when the gate electrode 6a is formed on the bottom surface of the recess 7 by aligning the mask with the recess 7 by a well-known method,
GaAs MES with recessed structure as shown in Figure 2
A FET is manufactured.

Ga As MES with recessed structure manufactured in this way
In the FET, the width L2 of the gate electrode 6a shown in FIG. 2 is about 1 μm, so the width of the recess 7 shown in FIG. L□ is at least 2 of the width L2 of the gate electrode 6a
~3 times, that is, about 2 to 3 μm is required.

For this purpose, for example, increase the distance between the source and drain by 4 to 5
If it is on the order of μm, the recess 7 will be formed in almost a large part of the channel region.

Therefore, the reverse breakdown voltage of the gate electrode 6a is not much different from the reverse breakdown voltage of the gate electrode 6 of the non-recessed GaAs MES FET shown in FIG.

For this reason, it is necessary to make the spacing between the source and drain somewhat wider than the spacing between the source and drain of a GaAs MES FET with a non-recessed structure.

Increasing the distance between the source and drain greatly increases the reverse breakdown voltage of the gate electrode 6a, but according to the results of experiments that measured the high frequency characteristics of GaAs MES FETs with such recessed structures, It has been found that even when the gain is lower and a drain voltage higher than the drain voltage of the non-recessed structure is applied, the output is almost the same as that of the non-recessed structure.

This is because the gap between the source and drain of a GaAs MES FET with a recessed structure is somewhat wider than that of a non-recessed structure, so the source resistance from the source electrode 4 to the gate electrode 6a is higher than that of a non-recessed structure. It is presumed that this is due to the large size.

It has also been confirmed through experimental results that it is effective for the width L□ of the recess 7 to be as close to the width L2 of the gate electrode 6a as possible in achieving high gain and high output.

This invention was made based on the above-mentioned experimental results, and is based on the above-mentioned experimental results.
Manufacturing of a recessed structure field effect transistor with high frequency characteristics, high gain, and high output with good workability by a method that can form an electrode with a width close to the opening width of the recess without aligning a mask with the recess. The purpose is to provide a method.

FIGS. 4a and 4e are cross-sectional views showing each manufacturing step of an embodiment of the manufacturing method according to the present invention.

First, as in the conventional method shown in FIGS. 3a and 3b, a buffer layer 2 and an active layer 3 are formed on the entire surface of a GaAs substrate 1.
is epitaxially grown, and a source electrode 4 is formed on the active layer 3.
and a drain electrode 5 is formed.

Next, a photoresist film 8 is formed on the source electrode 4 and the drain electrode 5, including the exposed surface of the active layer 3.
The photoresist film 8 on the portion of the surface where the recess 7 shown in FIG. 2 is to be formed is removed by photolithography to form a hole 9 (FIG. 4a).

Next, when the formed photoresist film 8 is immersed in water at a predetermined temperature for a predetermined time, the side walls of the holes 9 of the photoresist film 8 peel off from the active layer 3 and float up as shown in FIG. FIG. 4B [Then, using the photoresist film 8 in this state as a mask, the surface portion of the active layer 3 is removed by etching to form a recess 7 [FIG. 4C].

Next, a gate metal film 10 is deposited on the surface of the active layer 3 in the recess T and on the entire surface of the photoresist film 8 through the hole 9 (FIG. 4d).

Thereafter, by a well-known lift-off method, the photoresist film 8 and the gate metal film 10 deposited thereon are removed, and the gate electrode film 10 is left on the surface of the active layer 3 in the recess 7. 6a, a recessed GaAs MES FET according to this embodiment is manufactured (FIG. 4e).

Ga in the recessed structure manufactured by the method of this example
In the AsMES FET, a GaAsMES FET with a recessed structure manufactured by the conventional method explained in FIG.
Unlike ET, there is no need to consider the accuracy of mask alignment for forming the gate electrode 6a, so there is no need to make the spacing between the source and drain wider than that of the non-recessed structure shown in FIG.

Furthermore, since the degree of peeling of the side walls of the holes 9 of the photoresist film 8 can be controlled with good reproducibility by the water temperature and immersion time when the photoresist film 8 is immersed in water, the width LR of the recess 7 can be controlled. The width can be made close to the width L2 of the gate electrode 6a.

Therefore, the source resistance between the source electrode 4 and the gate electrode 6a can be reduced, and the recess 7 can be formed apart from the drain electrode 5.
Electric field concentration at the end of the drain electrode 5 is relaxed, and the reverse breakdown voltage of the gate electrode 6a can be increased.

Therefore, high gain and high output can be achieved.

Furthermore, in the method of the above embodiment, in order to form the recess 7 and form the gate electrode 6a in the recess 7, compared to the conventional method shown in FIG. It is possible to improve product yield and shorten working time.

As explained above, according to the method of the present invention, - a film is formed on the main surface of the semiconductor substrate in which the source electrode and the drain electrode are formed at a predetermined distance from each other on the main surface part; A photoresist film having holes provided at a predetermined distance from an electrode is immersed in water at a predetermined temperature for a predetermined time, and the sidewall portions of the holes of the photoresist film are peeled off from the main surface of the semiconductor substrate and floated. After this step, the main surface of the semiconductor substrate is etched away using the photoresist film as a mask to form a recess in the main surface. a step of depositing a gate metal film on the bottom surface of the recess, and removing the photoresist film and the gate metal film deposited thereon and leaving the gate metal film on the bottom surface of the recess to form a gate electrode. The degree of peeling of the side wall of the hole of the photoresist film is controlled by the water temperature and immersion time when the photoresist film is immersed in water, and the width of the opening of the recess is controlled. The gate electrode having a similar width can be formed on the main surface of the semiconductor body within the recess.

Therefore, it is possible to manufacture a semiconductor device having a recessed structure with high frequency characteristics, high gain, and high output.

Furthermore, since the gate electrode can be formed on the bottom surface of the recess without mask alignment with the recess, it is possible to shorten working time and improve product yield.

[Brief explanation of drawings]

Figure 1 shows a normal non-recessed GaAs MESFET.
Figure 2 is a cross-sectional view showing the structure of GaAsM with a recessed structure.
FIGS. 3a-c are sectional views showing the structure of an ES FET; FIGS. 3a-c are sectional views showing each manufacturing step of a conventional method for manufacturing a GaAs MESFET with a recess structure; FIGS. 4a-e are sectional views showing one implementation of the manufacturing method according to the present invention. FIG. 3 is a cross-sectional view showing each manufacturing step of the example. In the figure, 1 is a GaAs substrate, 2 is a buffer layer, 3 is an active layer, 4 is a source electrode, 5 is a drain electrode, 6.6a is a gate electrode, 7 is a recessed part, 8 is a photoresist film,
9 is a hole, and 10 is a gate metal film. Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims (1)

[Claims] 1- A first step of forming a photoresist film on the main surface of a semiconductor substrate in which a source electrode and a drain electrode are formed at a predetermined distance from each other on the main surface, a position intermediate between the source electrode and the drain electrode. a second step of forming holes in the photoresist film at a predetermined distance from both the electrodes;
a third step in which the photoresist film is immersed in water at a predetermined temperature for a predetermined period of time, and the side wall portions of the holes in the photoresist film are peeled off and floated from the main surface of the semiconductor substrate; After the step, a fourth step of etching away the main surface of the semiconductor substrate using the photoresist film as a mask to form a recess on the main surface, etching the recess on the photoresist film and through the hole in the photoresist film. a fifth step of depositing a gate metal film on the bottom surface of the recess, and removing the photoresist film and the gate metal film deposited thereon and leaving the gate metal film on the bottom surface of the recess; A method for manufacturing a field effect transistor, comprising a sixth step of forming an electrode.