JPS5850443B2 - Voltage/current conversion circuit - Google Patents

Description

[Detailed Description of the Invention] The present invention provides voltage and
Related to current conversion circuits.

Methods (principles) for converting voltage given as input into current include (a) a method that utilizes the mutual conductance of a differential amplifier;
).

(b) Differential voltage mirror
ialvoltage m1rror).

←→ Emitter degenerate amplifier
degenerated amplifier).

There are 03.

All of these methods convert differential input voltage to current, but methods (a) and (b) above have a limit on the range in which a current proportional to the input voltage can be obtained, so Suitable only for those that handle electricity.

On the other hand, the above method (/→) can handle input voltages of large signals as described below.

That is, the emitter degenerate of the above ←→
An edamplifier, ie, an emitter degeneration amplifier, uses an emitter degeneration resistor R1 as shown in the circuit example of FIG.

In this circuit, the current ■' flowing through the resistor R1 is obtained from the following equation.

However, LVBE (T1) and VBE (T2) are transistors T1. The voltage between the base and emitter of T2, ■in1゜■in2 is the input voltage, vT is the thermal voltage, and this vT is 30
It is about 26 mV at 00.

The numerical solution of the above equation (1) is set to R1=10, Ω and I=10
The results obtained under the conditions of 0μA1R1=100, Ω and I-100μA are shown in the graphs of FIGS. 2 and 3.

From the above results, the item in item 09 has the following properties.

(1) The voltage that can be used as an input is determined by the product of the emitter current ■ and the resistor R1.

That is, the maximum input voltage 1vin (max) can be (11) if the resistor R1 is made sufficiently large, I>>I', and the output current ■' is approximately proportional to the input voltage.

In other words, the second term on the right side of equation (1) can be ignored.

(m) Output current of emitter degeneration amplifier■1. (2) Due to these properties, the emitter degeneration amplifier can handle input voltages of large signals, and the mutual conductance (gain) can also be adjusted by the resistor R□.

This amplifier is therefore used in analog signal processing circuits.

Its best known application is the multiplicative kernel (mul
four-quadrant multiplier (four-quadrant multiplier)
er).

However, a drawback of the emitter degenerate amplifier is that increasing the conductance gm increases the error between the input voltage and the output current.

In other words, an optimal design considering the combination of resistance R1 that determines the output current, current ■, and the maximum value of input voltage "in," for example, R1 =
Even at 100 Ω, I=100 μA%, and yvinloV, there is an error of several percent.

This can also be inferred from the graph in FIG.

A circuit devised to reduce the error between the input voltage and output current was developed by van de Placier.
e plusche).

This circuit makes clever use of the Wilson source, and its principle diagram is shown in Figure 4.

That is, the collector potential of the transistor T3 is set to V.

0, the collector potential of transistor T6 is V.

2, the voltage ■ applied across the resistor R1.

becomes, and the input potential difference is precisely the resistance R1 Ru.

The current {circle around (1)} flowing through the resistor R1 is transmitted as follows, and errors other than the input voltage are small, which is improved over the equation (1).

Thus, the output current is taken out from the terminals out1 and out2.

That is, the current ■Ouj 1 ? ' □Hj 2 is the differential output current■.

ut is calculated as follows It will be done.

As can be seen from equation (6) above, the circuit shown in Figure 4 has improved linearity between input voltage and output current compared to the case of an emitter degenerate amplifier, and also has good results in terms of response speed. is obtained.

On the other hand, in order to increase the mutual conductance G, the resistance R
It is necessary to reduce the value of 1, but at the same time, the current source ■.

also needs to be made larger. Input current of this circuit ■in1
．． ■in2 is as follows, assuming that the PNP transistor current amplification factor of transistors T1 and T2 is βP.

Therefore, if the mutual conductance G is increased, the input bias current will increase.

This is a new problem that arose in Van de Plassie's circuit.

The present invention has been made in view of the above circumstances, and the linearity between the input voltage and output current of the circuit is improved not only over the above-mentioned emitter degeneration amplifier but also over the Van de Plassie circuit. The present invention aims to provide a voltage-to-current conversion circuit that can overcome the disadvantage of the large input current that existed in Van de Plassier's circuit.

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 5 shows the circuit of the same embodiment. Ql, Q4 in the diagram
are differential input stage transistors arranged symmetrically with a common emitter, 51 is a constant current source connected to the common emitter, 52 is a load element, and transistors Q2. Q3 constitutes a current mirror.

Q5 is an output transistor whose base is connected to the collector of transistor Q4 and whose emitter is connected to the base of Q4.

53 is a constant current source connected to the emitter of transistor Q5.

Similarly, Qs t Qto is a differential input stage transistor, 55 is a constant current source of its common emitter, and 56 is a transistor Q7. A load element consisting of Q9, this Q7. Q9 constitutes a current mirror.

Q6 is an output transistor, 57 is a constant current source, and R is Q4.
This is a reference resistor that connects the bases of 7Q8.

The left half 54 of FIG. 5 constitutes a voltage follower circuit.

That is, the base potential ■1n1 (input voltage) of the transistor Q1 is transmitted to the emitter of the transistor Q5.

The error between this ■in and the emitter potential of Q5 is about the offset voltage of the differential amplifier.

Similarly, the right half 58 constitutes a voltage follower circuit.

In other words, the input voltage (in2) of the transistor QIO is transmitted to the emitter of the transistor Q6.

After all, the potential difference between both ends of the resistor R is V.

is, and the current ■′ flowing through the resistor R is Find it as.

Also, the circuit output is a current ■ from the collectors of transistors Q5+Q6.

Extract as utl, ■out2.

If the current of the current source 53 is ■, then the differential output current "o"
Here, ut is the offset voltage V for the differential amplifier composed of transistors Q1 to Q5.

Let's find ff.

This causes an error in the linearity of this circuit.

That is, the collector currents of transistors Ql and Q4 are expressed as il, i
4, the common emitter current amplification factor of the lateral PNP transistor is βp, and that of the NPN transistor is βN, then this equation holds true.

The following example is used to estimate the error from equation (15) after calculating equation (14).

And the worst value of offset voltage is ■.

Since this is the case when ut1=2■o, the maximum offset voltage voff (max) at this time can be obtained as follows.

Considering the case of at the time of Next door s ■off (max) The error is Apply 16.4mV as becomes.

The error of the emitter degeneration amplifier under the same conditions is (1)
It is found to be 1.3% from the numerical solution of the equation.

In other words, the error of the circuit of FIG. 5 is an order of magnitude smaller than that of the emitter degenerate amplifier.

Furthermore, the input current of the circuit shown in Fig. 5 is 1n1 (transistor Q
1 input current), at this time, ■ini is almost constant.

On the other hand, in the emitter degenerate amplifier shown in FIG. 1, I· changes between -0 and 2 μA (VBH1 small → thick) nl in the same case.

Also, in the Van de Plassie circuit shown in Figure 4, ■in
1 is the case of the same constant, which is obtained from equation (9).

In the Van de Plassie circuit, if the transistor T1 is of the substratum (PNP) type, the above-mentioned ``in1'' becomes a little smaller, but it does not become smaller than several μA.

In other words, the circuit shown in FIG. 5 is superior to Van de Plassie's circuit in terms of input current.

Also, the error of this Plassier circuit is 1 mV or less, which is better than 16.4 mV in the same case.

The error caused by the offset voltage in the circuit shown in FIG. 5 can be improved by the circuit shown in FIG.

This circuit uses Wilson sources 52' and 56' as loads for a differential amplifier.

Offset voltage of this circuit ☆☆Voff is obtained in the same way as in the case of equation 04).

From this equation (22), ■.

ff is It is required as.

voff-0,422■T-10,9 [m■]This is (
L5) V determined by formula.

ff=16.4 mV, which is an improvement.

However, this is ■out1-2■o1 Io-10■1
Amu★ru in the worst case.

In order to further improve the offset voltage, the output transistors Q5 and Qa in FIG. 6 may be changed to Darlington transistors by adding transistors Q13 t Ql4 as shown in FIG.

In this case, the offset voltage ■. ff can be found by transforming equation (23).

This ■.

If ff is calculated using the 1-way formula, Voff=0.0
205VT=0.53 (m'V) This indicates that conversion can be achieved with an error of approximately the same order of magnitude as the error term of Van de Plassie's circuit (1 mV or less).

A circuit including transistor Q5/constant current source 53, transistor Q6', and constant current source 55 shown by dotted lines in FIG.
The circuit according to ' shows yet another offset improvement method.

That is, if we pay attention to the left half 54 of FIG. 5, the base current of the output transistor Q5 is the collector current IC(Q4) of the transistor Q4, which is the collector current IC(Ql) of the transistor Q1, and the collector current IC(Q4) of the transistor Q1. -I.

(, 4) (offset cause).

Therefore, Q5, which is symmetrical to transistor Q5 and constant current source 53,
5' and a constant current source 53' are connected to the collector of the transistor Q1 so that the relationship 'c(Ql)-'C(Q,)' is obtained.

This means that the transistor Qg and constant current source 53 in FIG.
The same applies to the circuit of ', Q6', and the constant current source 55', and in FIG. 7, transistors Q5'>Q13' are also Darlington in accordance with transistors Q57Q13.

FIG. 8 shows, for example, the voltage/current conversion circuit shown in FIG. 5, which is applied to a single output voltage/current conversion circuit by adding current mirrors 51, 62, and 63.

The input terminal of the transistor Q□5 of the current mirror 61 is connected to the collector of the output transistor Q5, the input terminal of the transistor Q200A of the current mirror 63 is connected to the collector of the output transistor Q6, and the input terminal of the transistor Q17 + Qts of the current mirror 62 is connected to the collector of the output transistor Q6. The collectors are transistors Q1a and Q of current mirrors 61 and 63.
Since it is connected to the collector of 19, the output current is ■.

As in the case of formula 03), ut is becomes.

That is, due to current mirror operation, the emitter current of transistor Q5 and the collector current of transistor Q16 are both I.

+I'C- is present, and the emitter current of transistor Q6, collector current of Q19, and collector current of Q1□ are all ■.

-■', and the current I' of the resistor R is So, the output current ■.

ut(2■') can be found as equation (251).

In Figure 9, the NpN input in Figure 8 is changed to a PNP input format. In this case, all the pot transistor formats are in the opposite relationship to those in Figure 8, so the same go signs are used for corresponding parts. Add a dash and omit the explanation.

The circuits shown in FIGS. 8 and 9 can be written as a symbol as shown in FIG. 10a.

Here it becomes.

This circuit is a single output type, but if a load resistor RL is connected to the output terminal as shown in Figure 10, the output voltage V will be proportional to the input voltage.

ut is obtained. In other words, a voltage proportional to the difference between the two input voltages is obtained as an output.

This can be used as a simple subtraction circuit.

Also, if the configuration is as shown in Figure 10C, Thus, an adder circuit is obtained.

Here, the error of the current mirror used in the single output type voltage/current conversion circuit will be explained with reference to FIG. 11a.

That is, the input current ii and the output current i of the current mirror.

is the current mirror, and the output current ratio is i.

Ideally, /11=1, but in the case of FIG. 11a, there is an error of 2/β.

On the other hand, in the Wilson source shown in FIG. 11, the error in the output current ratio is 2/β2, which is smaller than that in FIG. 11a (β) (2).

In other words, the Wilson source is an improved current mirror.

This Wilson sauce 52', 56'. 61', 6
FIG. 12 shows a single output voltage/current circuit constructed using 3'.

Next, an example of application to a two-output voltage/current conversion circuit will be explained.

This is a voltage/current conversion circuit that takes out output currents of opposite polarity.

Transistor Q2 is added to the single output voltage-current conversion circuit described above.
FIG. 13 shows a device in which Q4 to Q27 are added and output terminals of opposite polarity are provided.

This circuit has V CT (voltage −t. cur
It has the same functionality as what is called a rent transactor (rent transactor), but has a wider range of applications than the single output version.

In FIG. 13, transistor Q24 is a current mirror 61 whose base is commonly connected to Q10, transistors Q257 and Q26 constitute a current mirror 65, and transistors Q2
The collector of 5 and the collector of Q24 are connected in phase, and the collector of Q26
t Since the collector of Q27 is phase-connected and the base of Q27 is commonly connected to the base of Q20, the output current I.

ut becomes.

That is, by the current mirror operation, the transistors Q5,
The 1V vector currents of Q24 t Q16 + Q26 are both ■.

+■' and transistor Q1□. Q19, Q
207 Both collector currents of Q27 are ■.

-■', and the current of the resistor R is So, the output current ■.

ut (This is what you can find.

±2■') is the formula (31) ☆ ☆ The symbol of the above VCT is shown in Fig. 14.

FIG. 15 shows a two-output voltage/current conversion circuit in which the current mirror circuit is constructed of a Wilson source and the output transistor is constructed of a Darlington transistor.

Here, Q28 to Qao are newly added transistors.

Next, a well-known multiplier core (multiplier core
) The circuit is shown in FIG.

Here, the following equation holds true for the current indicated by the arrow.

The sum of the currents is calculated at the emitters of transistors Q2A and Q2B.

Similarly, regarding Q3A +Q3B, it can be seen from equations (32) and (34) that a component of the product of currents (lxiy) appears.

Also, although I have already mentioned the emitter degenerate amplifier, I will explain the relationship between voltage and current in this circuit in the 17th section.
Define it as shown in the figure (.

Then, if we ignore the second term on the right-hand side of the equation (4) and use a pair of the circuit shown in FIG. 16 and the circuit shown in FIG.
multiplier) is formed.

In this multiplier, the output voltage e. becomes ★.

That is, if the input voltage of the differential amplifier 710 is , substitute equation (48) into equation (47).

That is, the output voltage e.

is the two input voltages (x.x2) It can be seen that it is proportional to the product of (yt 72 ).

The disadvantage of the multiplier shown in FIG. 18 is that the input bias current (in) of the differential input section is large.

In other words, the input voltage that can be handled is determined by the value of ■RX, and therefore, in order to obtain a sufficient analog input voltage range, it is necessary to set the current source ■ to a large value. It doesn't get smaller.

Further, in the circuit of FIG. 18, the output voltage e. The accuracy is about 1% at full scale (1OV).

This is because an error term, that is, a logarithmic ring on the right side of equation (42), exists in the current conversion of the emitter degeneration amplifier.

In order to improve the above-mentioned drawbacks, FIG. 19 shows the voltage/current conversion circuit of FIG.
udrant analog multiplier
).

In this multiplier, the input current can be made small as explained in Fig. 5, and the error in current conversion is the input offset voltage of the differential amplifier, which is smaller than in the case of an emitter degenerate amplifier. The offset voltage can be made sufficiently small by performing simple operations such as changing the load element of the differential amplifier to a Wilson source or changing the output transistor to a Darlington configuration.

Note that the present invention is not limited to the above-mentioned embodiments. For example, the NPN input format as shown in FIG.
The operation of changing to the P input type can also be performed in each embodiment, and the load element of the differential amplifier shown in FIG. 7 can be made into a Wilson source, the output transistor can be made into a Darlington configuration, The operation of reducing the offset voltage by adding a circuit symmetrical to the output transistor can also be applied to the circuits of each example.

Further, the constant current source of the differential amplifier may be a current source composed of a resistor, the load element may be of a structure other than a current mirror, and the reference resistor R may be an impedance element other than the embodiment.

As explained above, according to the present invention, the input current of the differential amplifier section can be reduced, and the error in the output voltage with respect to the input voltage can be minimized, so that a practical voltage/current conversion circuit can be provided. be.

[Brief explanation of drawings]

Figure 1 is a diagram of the emitter degeneration amplifier circuit, Figures 2 and 3 are characteristic diagrams of the same circuit, and Figure 4 is an improved version of the same circuit.
Plassier's circuit diagram, FIG. 5 is a circuit diagram of one embodiment of the present invention, FIGS. 6 to 9 are circuit diagrams of other embodiments of the present invention,
10a to 10C are circuit diagrams showing application examples of the present invention;
Figure a is a circuit diagram of a current mirror;
Source circuit diagrams, Figures 12 to 15 are circuit diagrams of different embodiments of the present invention, Figure 16 is a multiplication branch circuit diagram, and Figure 17 is a multiplication branch circuit diagram.
18 is a diagram of an emitter degeneration amplifier circuit, FIG. 18 is a multiplication circuit diagram using the same circuit, and FIG. 19 is a circuit diagram of an application example of the present invention. Ql, Q4. Q8. Qlo...Differential input stage element, Q5. Q6...Output transistor, Q5'
, Q6'...offset prevention transistor,
51, 55...constant current source, 52...
Current mirror, 53, 57... Constant current source, R
...Resistor, 52', 56'...Wilson source, Ql3...Transistor, 61
゜62.63・・・・・・Current mirror.

Claims (1)

[Claims] 1. First and second differential input stage elements having a common emitter and arranged symmetrically to each other, a current source connected to the common emitter of the elements, and a current source of the differential input stage elements. a load element disposed on the collector side, a base of the first differential input stage element, an output transistor whose emitter and base are connected between the collectors, and a constant current source connected to the emitter of the transistor, respectively. means for applying an input voltage between the bases of the 20th differential input stage elements of the first and second circuits; an impedance element disposed between the emitters of the transistors for converting the input voltage into a current according to the value thereof, and a current corresponding to the current flowing through the impedance element is supplied to the eleventh and second circuits. A voltage/current conversion circuit characterized in that output is taken out from the collector of at least one of the output transistors. 2. First and second differential input stage elements having a common emitter and arranged symmetrically to each other, a current source connected to the common emitter of the elements, and a current source arranged on the collector side of the differential input stage element. A load element, an output transistor having an emitter and a base 7 connected between the base and collector of the first differential input stage element, and a constant current source connected to the emitter of the transistor, respectively. 1. A second circuit, means for applying an input voltage between the bases of the 20th differential input stage elements of the first and second circuits, and emitters of output transistors of the first and second circuits; an impedance element arranged between the collectors of the output transistors of the first and second circuits for converting the input voltage into a current according to the value thereof; A voltage/current conversion circuit comprising a current mirror circuit for extracting current.