JPS5850444B2 - auto-balanced amplifier circuit - Google Patents
auto-balanced amplifier circuitInfo
- Publication number
- JPS5850444B2 JPS5850444B2 JP533476A JP533476A JPS5850444B2 JP S5850444 B2 JPS5850444 B2 JP S5850444B2 JP 533476 A JP533476 A JP 533476A JP 533476 A JP533476 A JP 533476A JP S5850444 B2 JPS5850444 B2 JP S5850444B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- amplifier
- balanced
- extracts
- amplifiers
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000000284 extract Substances 0.000 claims 6
- 238000006243 chemical reaction Methods 0.000 description 14
- 238000010586 diagram Methods 0.000 description 4
- 230000003247 decreasing effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000010355 oscillation Effects 0.000 description 2
- 230000002194 synthesizing effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Amplifiers (AREA)
- Superheterodyne Receivers (AREA)
Description
【発明の詳細な説明】
この発明は2人力信号の差出力を得るための平衡増幅回
路に関するものであり、特に平衡線周波数変換回路の中
間周波出力の合成に用いられた場合に周波数変換回路を
含めて全体として良好な平衡を保つ自動平衡増幅回路に
関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a balanced amplifier circuit for obtaining a difference output between two human input signals, and particularly to a balanced amplifier circuit for obtaining a differential output of two human input signals, and particularly for a frequency conversion circuit when used for synthesizing intermediate frequency outputs of a balanced line frequency conversion circuit. This invention relates to an automatically balanced amplifier circuit that maintains good balance as a whole.
平衡線周波数変換回路は雑音指数の低い周波数変換回路
として広く用いられている。Balanced line frequency conversion circuits are widely used as frequency conversion circuits with a low noise figure.
特に局発信号源自身が大きな雑音を発生するような、例
えばインバット発振器のような場合には平衡形にするこ
とによる雑音低減効果は顕著である。Particularly in cases where the local oscillator itself generates a large amount of noise, such as an in-bat oscillator, the noise reduction effect of using a balanced type is significant.
しかし、このような低雑音性が得られるのは2つの周波
数変換器および両出力を合成する・・イブリッド回路、
あるいは差動増幅器のバランスが完全に取れている場合
であり、バランスがくずれると特性は急激に劣化する。However, such low noise can be obtained by combining two frequency converters and both outputs... an hybrid circuit,
Alternatively, the differential amplifier may be perfectly balanced, and if the balance is lost, the characteristics will deteriorate rapidly.
一般に周波数変換器の変換損失は局発電力の影響を受け
るが、2つの周波数変換器における局発電力の影響を充
分にそろえることは極めて困難である。Generally, the conversion loss of a frequency converter is influenced by local power, but it is extremely difficult to sufficiently equalize the effects of local power in two frequency converters.
つまり局発電力が充分に安定でないと充分な低雑音特性
が得られなくなる。In other words, unless the local power is sufficiently stable, sufficient low-noise characteristics cannot be obtained.
本発明の目的は平衡線周波数変換回路に用いて自動的に
平衡を保ち、低雑音特性を実現する平衡増幅回路を提供
することにある。An object of the present invention is to provide a balanced amplifier circuit that can be used in a balanced line frequency conversion circuit to automatically maintain balance and achieve low noise characteristics.
以下図面を用いて本発明について詳細に説明する。The present invention will be explained in detail below using the drawings.
第1図は従来の平衡線周波数変換回路の一例を示すブロ
ック図であり、端子1から加わった入力信号はハイブリ
ッド2によって2等分され周波数変換器3,4へ加わる
。FIG. 1 is a block diagram showing an example of a conventional balanced line frequency conversion circuit, in which an input signal applied from a terminal 1 is divided into two equal parts by a hybrid 2 and applied to frequency converters 3 and 4.
また同時に局発信号源5からの局発信号もハイブリッド
2によって2等分され周波数変換器3,4へ加わる。At the same time, the local oscillation signal from the local oscillation signal source 5 is also divided into two equal parts by the hybrid 2 and applied to the frequency converters 3 and 4.
但しハイブリッドの位相特性により周波数変換器3と4
へ加わる局発信号の位相は互いに逆相である。However, due to the phase characteristics of the hybrid, frequency converters 3 and 4
The phases of the local oscillator signals applied to are opposite to each other.
従って周波数変速器3,4から得られる入力信号と局発
信号の差周波数の中間周波信号は互に逆相となる。Therefore, the intermediate frequency signals of the difference frequency between the input signal and the local signal obtained from the frequency changers 3 and 4 have opposite phases.
これら中間周波信号は端子7,8を通してハイブリッド
トランス6で合成され端子9に現われ中間周波増幅器1
0で増幅された後出力端子11に得られる。These intermediate frequency signals are synthesized by a hybrid transformer 6 through terminals 7 and 8, and appear at a terminal 9, where they are output to an intermediate frequency amplifier 1.
After being amplified by 0, it is obtained at the output terminal 11.
このとき局発信号源に含まれる雑音は端子7,8へ同位
相で現われるためハイブリッドトランス60作用で相殺
され端子9には現われない。At this time, the noise contained in the local signal source appears at the terminals 7 and 8 in the same phase, so it is canceled out by the action of the hybrid transformer 60 and does not appear at the terminal 9.
これが従来の平衡線周波数変換回路が低雑音特性を示す
動作原理である。This is the operating principle by which conventional balanced line frequency conversion circuits exhibit low noise characteristics.
しかし雑音が完全に相殺されるためには周波数変換器3
゜4の変換損失が全く等しく、かつハイブリッドトラン
ス6のバランスが良好でなくてはならない。However, in order to completely cancel out the noise, the frequency converter 3
The conversion losses of .degree. 4 must be exactly the same, and the balance of the hybrid transformer 6 must be good.
しかし前述したように一般にこのバランスを良好に保つ
ことは必ずしも容易なことではない。However, as mentioned above, it is generally not always easy to maintain this balance well.
第2図は本発明の一実施例の構成を示すブロック図で、
12.13は信号の入力端子であり、この自動平衡増幅
回路を平衡線周波数変換回路の一部として用いた場合に
は、第1図の端子7,8に対応する端子である。FIG. 2 is a block diagram showing the configuration of an embodiment of the present invention.
Reference numerals 12 and 13 are signal input terminals, which correspond to terminals 7 and 8 in FIG. 1 when this automatic balanced amplifier circuit is used as a part of a balanced line frequency conversion circuit.
端子12,13から加わった信号は利得制御が可能な増
幅器14.15で増幅され、画壇幅器出力の和が加算回
路16、差が減算回路17で取られる。The signals applied from the terminals 12 and 13 are amplified by gain-controllable amplifiers 14 and 15, and the sum of the outputs of the stage width amplifiers is taken by an adder circuit 16, and the difference is taken by a subtracter circuit 17.
差信号は端子18から本平衡増幅回路の出力信号として
出力されると同時に乗算回路19において前記和信号と
の間で積が取られる。The difference signal is output from the terminal 18 as an output signal of the balanced amplifier circuit, and at the same time is multiplied by the sum signal in the multiplier circuit 19.
この積信号は増幅器20で増幅され低域通過フィルタを
介して前記増幅器14゜150利得制御信号として帰還
される。This product signal is amplified by an amplifier 20 and fed back through a low pass filter as a gain control signal for the amplifier 14.150.
この回路において今入力端子12,13にそれぞれs+
n、α(−s+n)なる信号が加わったとする。In this circuit, input terminals 12 and 13 each have s+
Suppose that signals n and α(-s+n) are added.
ここでSは所望の中間周波信号、nは雑音であり、αは
2つの周波数変換器のバランスの程度を示す係数であり
、完全にバランスが取れている場合には1となる量であ
る。Here, S is a desired intermediate frequency signal, n is noise, and α is a coefficient indicating the degree of balance between the two frequency converters, and is a quantity that is 1 when the two frequency converters are perfectly balanced.
この係数αがSとnに対して共通となっているのは周波
数変換器の変換損失は信号に対しても雑音に対しても対
等に働くためである。The reason why this coefficient α is common to S and n is that the conversion loss of the frequency converter acts equally on both signals and noise.
増幅器1415の利得をそれぞれA1、A2とすると加
算回路16の出力はA1(s+n)十A2α(−8+n
)となり、減算回路17の出力はA1(s+n)−A2
α(−8+n)となる。Assuming that the gains of the amplifiers 1415 are A1 and A2, the output of the adder circuit 16 is A1 (s+n) + A2α (-8+n
), and the output of the subtraction circuit 17 is A1(s+n)-A2
α(-8+n).
従ってこれら両信号の積は(A1−cc2A2) (s
2+n2) + (AF+α2Aj ) 4 sn
となる。Therefore, the product of both these signals is (A1-cc2A2) (s
2+n2) + (AF+α2Aj) 4 sn
becomes.
この信号を増幅し低周波成分のみを取り出すと、第2項
は平均値Oの雑音成分であり低域通過フィルタでほとん
ど阻止される。When this signal is amplified and only the low frequency component is extracted, the second term is a noise component with an average value of O and is almost blocked by the low pass filter.
一方策1項の(s2+n2)の項は信号と雑音の電力の
和を意味するため、この平均電力に比例する定数kが係
数としてかかった電圧K(AZAζα2)が得られる。On the other hand, since the term (s2+n2) in the first option means the sum of the power of the signal and the noise, a voltage K (AZAζα2) is obtained in which a constant k proportional to this average power is applied as a coefficient.
この電圧が正の場合には増幅器15の利得を上げ、増幅
器14の利得を下げ、負の場合には増幅器14の利得を
上げ、増幅器15の利得を下げるような制御を行なえば
定常状態ではほぼAI’ 一人:α2 = 0となる。If this voltage is positive, the gain of the amplifier 15 is increased and the gain of the amplifier 14 is decreased, and if this voltage is negative, the gain of the amplifier 14 is increased and the gain of the amplifier 15 is decreased. AI' alone: α2 = 0.
つまりA1穴2α(−A) となる。In other words, A1 hole 2α(-A).
この関係が成立しているときには減算回路17の出力は
2Asとなり雑音nは含まれない。When this relationship holds, the output of the subtraction circuit 17 becomes 2As and does not include noise n.
つまり周波数変換器の不平衡が補正され全体として平衡
のとれた周波数変換回路を実現できる。In other words, the unbalance of the frequency converter is corrected, and a frequency conversion circuit that is balanced as a whole can be realized.
以上の実施例の説明では増幅器14,15共に互いに逆
の方向に利得制御をする場合を示したが、これは必ずし
も必要でなくどちらか一方の増幅器の利得制御を行なう
だけでも本発明の目的を達することができる。In the above description of the embodiment, a case has been shown in which the gains of the amplifiers 14 and 15 are controlled in opposite directions, but this is not necessarily necessary, and the purpose of the present invention can be achieved by controlling the gain of either one of the amplifiers. can be reached.
以上述べたように本発明によれば平衡線周波数変換回路
に用いて、そのバランスを自動的に補正し常に雑音指数
を低く保つことができる自動平衡増幅回路を得ることが
でき、インバット発振器など雑音の大きい発振器を局発
信号源とする通信装置に用いて極めて有効である。As described above, according to the present invention, it is possible to obtain an automatically balanced amplifier circuit that can be used in a balanced line frequency conversion circuit to automatically correct the balance and keep the noise figure low at all times. This is extremely effective for use in communication equipment that uses a large oscillator as a local signal source.
第1図は従来の平衡線周波数変換回路の一例を示すブロ
ック図、第2図は本発明の一実施例の構成を示すブロッ
ク図であり、図中12,13は信号の入力端子、13は
出力端子、14.15は利得制御が可能な増幅器、16
は加算回路、17は減算回路、19は乗算回路、20は
増幅器、21は低域通過フィルタである。FIG. 1 is a block diagram showing an example of a conventional balanced line frequency conversion circuit, and FIG. 2 is a block diagram showing the configuration of an embodiment of the present invention. In the figure, 12 and 13 are signal input terminals; Output terminal, 14.15 is an amplifier capable of gain control, 16
17 is a subtraction circuit, 19 is a multiplication circuit, 20 is an amplifier, and 21 is a low-pass filter.
Claims (1)
増幅器の出力の差を平衡出力として取り出す平衡増幅回
路において、両増幅器出力の差を取り出す差回路と、両
増幅器出力の和を取り出す和回路と、差回路出力と和回
路出力の積を取り出す乗算回路と、乗算回路出力信号の
低周波信号成分を取り出す回路とを備え、前記増幅器の
少なくとも一方を利得可変の増幅器とし、該増幅器の利
得を前記低周波信号成分を取り出す回路出力で制御する
ように構成したことを特徴とする自動平衡増幅回路。In a balanced amplifier circuit that includes an independent amplifier for each of the 12 human power signals and extracts the difference between the outputs of both amplifiers as a balanced output, there is a difference circuit that extracts the difference between the outputs of both amplifiers, and a sum circuit that extracts the sum of the outputs of both amplifiers. , a multiplier circuit that extracts the product of the difference circuit output and the sum circuit output, and a circuit that extracts the low frequency signal component of the multiplier circuit output signal, at least one of the amplifiers is a variable gain amplifier, and the gain of the amplifier is set to the An automatic balancing amplifier circuit characterized in that it is configured to be controlled by a circuit output that extracts low frequency signal components.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP533476A JPS5850444B2 (en) | 1976-01-20 | 1976-01-20 | auto-balanced amplifier circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP533476A JPS5850444B2 (en) | 1976-01-20 | 1976-01-20 | auto-balanced amplifier circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5289046A JPS5289046A (en) | 1977-07-26 |
| JPS5850444B2 true JPS5850444B2 (en) | 1983-11-10 |
Family
ID=11608327
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP533476A Expired JPS5850444B2 (en) | 1976-01-20 | 1976-01-20 | auto-balanced amplifier circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5850444B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0372378A (en) * | 1989-08-12 | 1991-03-27 | Mita Ind Co Ltd | Paper refeeding device for composite image forming device |
| JP2008079097A (en) * | 2006-09-22 | 2008-04-03 | Sharp Corp | Amplifier circuit and electronic device |
-
1976
- 1976-01-20 JP JP533476A patent/JPS5850444B2/en not_active Expired
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0372378A (en) * | 1989-08-12 | 1991-03-27 | Mita Ind Co Ltd | Paper refeeding device for composite image forming device |
| JP2008079097A (en) * | 2006-09-22 | 2008-04-03 | Sharp Corp | Amplifier circuit and electronic device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5289046A (en) | 1977-07-26 |
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