JPS5850465B2 - Timing circuit of PCM transmission line repeater - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a timing circuit built into a transmission line repeater for baseband PCM transmission systems, carrier wave PCM transmission systems, and the like.

A transmission line repeater in the PCM transmission system has three functions: waveform equalization, retiming, and identification reproduction.

The timing of these three functions is performed by a timing circuit, but the timing circuit of a conventional PCM transmission line repeater includes a folding circuit to generate the bright line spectrum of the clock component from the PCM pulse train after waveform equalization, and a It consists of a resonant circuit that extracts the clock component and an amplitude limiting circuit that keeps the amplitude of the extracted clock component constant, and as the resonant circuit, a normal LC tank is used in the relatively low frequency range.
In the high frequency range, cavities, which are LC parallel resonators in principle, edge cal resonators, thin film spiral resonators, etc. are used.

As is well known, the clock frequency component that is the output of the timing circuit of such a conventional PCM transmission line repeater has phase noise (hereinafter referred to as jitter) that depends on pattern fluctuations of the equalized pulse train, and has N stages. It is known that the rms value σN of the jitter accumulated in the second PCM transmission line repeater is proportional to N to the 1/2 power.

Since the number of PCM transmission line repeaters inserted from the transmission end to the reception end of the transmission line is usually about 100, the rms value of jitter at the reception end is 30 times the rms value of jitter at the PCM transmission line repeater. The value becomes twice as large, significantly degrading the signal quality after demodulation.

As is well known, when using the timing circuit of a conventional PCM transmission line repeater, the jitter rms value σN after N repeaters increases in proportion to the 1/2 power of N, as described above. It is based on the fact that jitter accumulates systematically in each repeater.

An object of the present invention is to provide a new timing circuit for a PCM transmission line repeater that improves the above-mentioned drawbacks of the conventional timing circuit for a PCM transmission line repeater.

The configuration of the present invention will be explained in detail below based on examples.

A general embodiment of the invention is shown in FIG.

That is, the timing circuit of the PCM transmission line repeater according to the present invention is constituted by a cascade connection of a folding circuit indicated by 1, a resonant circuit using a surface acoustic wave filter indicated by 2, and an amplitude limiting circuit indicated by 3. .

In FIG. 1, a received equalized pulse train is input to an input terminal 4, and a bright line spectrum of a clock component is generated in a folding circuit 1.

Note that as the folding circuit, a so-called absolute value folding circuit that outputs the absolute value of a difference signal between the input signal and a preset DC level, or a so-called square folding circuit that outputs the square value of the difference signal is used. However, as is well known, such non-linear circuits can be easily realized using semiconductor diodes.

Now, the clock frequency component generated in this way is extracted by a resonant circuit using a surface acoustic wave filter shown by 2, and then the amplitude is kept constant by an amplitude limiting circuit shown by 3, and the output is shown by 5. At the end, a jittered clock fraction is output.

As is well known, the surface acoustic wave filter described above generally has a constant delay time τ, so in the timing circuit of the PCM transmission line repeater according to the present invention, when a received equalization pulse is input at a certain time, The clock frequency component excited by the pulse is output with a delay of τ.

Therefore, in the repeater identification and regeneration circuit using the timing circuit of the PCM transmission line repeater according to the present invention, when identifying and reproducing a pulse at a certain time, the clock frequency excited by a pulse that is τ in the past than that pulse is used. The components will be retimed.

This shows that it has the effect of equivalently randomizing the received equalized pulse train as far as jitter transmission is concerned.

Therefore, by using the timing circuit of the PCM transmission line repeater according to the present invention, it is possible to suppress the systematic accumulation of jitter at the time of multiple repeaters, and the delay time τ can be
If the rms jitter σN after N relays is set sufficiently large within a small range compared to the build up time, the rms jitter σN after N relays can be made to follow a gentle additive law proportional to N to the 1/4th power.

A more specific embodiment of a timing circuit for a PCM transmission line repeater according to the present invention is shown in FIG. 2, and an example of a surface acoustic wave filter used in the present invention is shown in FIG.

In FIG. 2, 6 is a normal folding circuit, and 7 is a normal amplitude limiting circuit.

The equalized pulse train entering the input terminal 24 is folded back by the folding circuit 6, and then connected to the transistor 12 via the bypass capacitor 8, and the resistors 9, 10, 11, 13, 14 and '
The signal is amplified by a buffer amplifier consisting of a bypass capacitor 15.

The output of the buffer amplifier passes through a surface acoustic wave filter 16, and the clock frequency component is extracted with a delay of a delay time τ.
A clock frequency component whose amplitude is amplified by a post-stage amplifier consisting of 2 and input to the amplitude limiting circuit 7 via a bypass capacitor 23 to have a constant amplitude is obtained at an output terminal 25.

Note that 26 is a terminal connected to a positive power source, and 27 is a terminal connected to a negative power source.

In the specific embodiment shown in FIG. 2, the equalized pulse train can be equivalently randomized as far as jitter transmission is concerned by appropriately setting the delay time τ of the surface acoustic wave filter as described above.

Note that if the matching impedance of the input and output of the surface acoustic wave filter 160 is Ro, it is necessary to set the resistors 11 and 17 to Ro, but the matching impedance Ro of the surface acoustic wave filter can be changed within a relatively wide range. Therefore, the collector load of the transistor 12 can be lightened by selecting Ro to have a relatively large impedance.

Furthermore, since the input and output of the surface acoustic wave filter, the input and the ground, and the output and the ground are all isolated in terms of direct current, there is no need to insert bypass capacitors at points A and B in FIG.

Next, the surface acoustic wave filter used in the present invention will be explained in detail based on FIG.

In FIG. 3, reference numeral 31 denotes a piezoelectric substrate, and from the viewpoint of temperature characteristics, ST-cut (42°, 75° rotated Y-cut) crystal is a particularly desirable material for the surface acoustic wave filter used in the present invention.

On this substrate 31, interdigital electrodes 32 consisting of a large number of parallel linear conductors are provided so that the pitch thereof is 1/2 of the surface acoustic wave wavelength at the clock frequency, and every other electrode is located at a terminal on both sides. Connected to electrodes 34.35.

When a clock pulse train is applied between the terminal electrodes 34 and 35, it is converted into a surface acoustic wave by the input interdigital electrode 32, propagates through the propagation path 38, and is generated by the output interdigital electrode 33 having the same structure as the input interdigital electrode. It is converted back into an electrical signal and taken out by terminal electrodes 36, 37.

Although surface acoustic waves are also radiated in the opposite direction to the propagation path by the input interdigital electrode 32, they can be prevented from entering the propagation path 38 by absorbing them with a suitable absorbing material or the like.

Now, if both the input and output interdigital electrodes are composed of (2M+1) strips, the transfer function of this filter is H□□□
) is known to be approximately given by.

In this example, A is a proportionality constant, f is a frequency, and fo is a center frequency of the filter f - f.

number, x=Mπ.

An example is 400f.

Consider a MHz PCM relay system.

The surface acoustic wave velocity of the ST cut crystal in the X-axis direction is approximately 315
0 m/s, the surface acoustic wave wavelength at 400 MHz is approximately 79 μm.

If the strip width and the gap of the interdigital electrodes are chosen to be equal, the strip width is approximately 2 μm, and such an electrode pattern can be created by conventional photoetching techniques.

From formula (1), the number of strips of input and output interdigital electrodes is 2.
01 (that is, N=100), 157 is obtained as the Q of the resonant circuit.

What should be noted here is that the Q and phase characteristics of the resonant circuit are independent in principle, and are significantly different from conventional resonant circuits.

From equation (1), if the number of electrode strips is increased, a resonant circuit with a higher Q can be realized, but on the other hand, the symmetrical bandpass characteristic is distorted due to the acoustic impedance discontinuity between the electrode strip part and the part without electrodes. , problems such as an increase in multiple reflected echoes occur.

Therefore, it is not possible to increase the number of electrode strips unnecessarily, but it is possible to increase the number of electrode strips to several hundreds.

Note that if the reflected echo is a problem, it can be suppressed to a practically sufficient degree by using a double electrode structure.

The allowable clock frequency variation in the PCM relay system is 10
For example, if the delay time τ is 1 μS (distance between input and output interdigital electrodes is 3.15 mm), then (1
), the phase variation of the surface acoustic wave filter is 1.4°.

In addition, the phase fluctuation due to temperature change is caused by ST-cut crystal (X
△φ/φ-31,5X10~9(
It is known that T-25)2 (2).

If we take O~50'C as the temperature range, △φ/φ-2
,OX1. O', and the phase variation Δφ is 2.8° for the above numerical example.

Therefore, it can be seen that the surface acoustic wave filter has sufficient stability as a resonant circuit of a PCM transmission line repeater.

The case where the timing circuit of the PCM transmission repeater according to the present invention is applied to a PCM transmission line repeater using a self-timing method has been described above, but the present invention can also be applied to a PCM transmission line repeater using an external timing method using a bicot weight. The applicability is clear.

When the timing circuit of the present invention is applied to a PCM transmission line repeater, it has the effect of significantly reducing the accumulation of rms jitter during multiple repeaters compared to conventional circuits, and the surface acoustic wave filter used in the present invention is as described above. Since the circuit according to the present invention is formed flatly on a crystal substrate as described in 1, it is very suitable for hybrid IC formation and can be significantly miniaturized.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a general embodiment of the present invention, in which 1 is a folding circuit, 2 is a resonant circuit using a surface acoustic wave filter, and 3 is an amplitude limiting circuit. FIG. 2 is a circuit diagram showing a specific embodiment of the present invention,
6 is a folding circuit, 16 is a surface acoustic wave filter, and 7 is an amplitude limiting circuit. FIG. 3 is an overhead view showing an example of a surface acoustic wave filter used in the present invention, and 31 is an ST-cut crystal substrate;
Reference numerals 2 and 33 indicate input/output interdigital interdigital electrodes for mutually converting electric signals and surface acoustic waves, and 38 indicates a propagation path for the surface acoustic waves.

Claims (1)

[Claims] 1. A folding circuit that generates a bright line spectrum of a clock frequency component from a received equalized pulse train, a resonant circuit using a surface acoustic wave filter that extracts the clock frequency component from the output of the folding circuit, and an output of the resonant circuit. A timing circuit for a PCM transmission line repeater, which is characterized by being connected in cascade with an amplitude limiting circuit that makes the amplitude of a clock frequency component constant, and which reduces the accumulation of rms jitter during multiple repeaters.