JPS5850518B2 - frequency converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION When applying gate signals to various switching elements of a thyristor, it has been recognized that the gate signals are often applied at unnecessary times in terms of signal processing, resulting in increased gate loss and A situation arises in which the power consumption loss of the power transformer increases.

Therefore, the present invention provides low frequency AC voltage (hereinafter referred to as VIN)
The object of the present invention is to obtain a gate trigger circuit that can easily form a gate signal with an appropriate pulse width depending on the polarity and can apply a sufficient reverse bias voltage between the gate and cathode of a switching element.

A description will be given below based on one embodiment.

FIG. 1 shows the configuration of a frequency conversion device.

A high frequency bypass capacitor 2 is connected in parallel with the low frequency AC power supply 1, and a choke coil 3, a commutating capacitor 6, and a commutating inductor 7 are connected in series from one terminal A of the capacitor 2, and then connected to the other terminal of the capacitor 2. Connect to terminal A of the

A switching semiconductor block 4 including two thyristors 41 and 42 connected in antiparallel is connected in parallel to the resonant circuit.

FIG. 2 shows a control circuit block diagram.

Detecting the voltage between the terminals of the switching semiconductor block 4,
Each output pulse of the first pulse start timing forming circuit 8 and the first pulse stop timing forming circuit 11, which form the start timing pulse for forming the first pulse, is
The pulse forming circuit 10 is manually operated to obtain a first pulse waveform.

The first pulse stop timing forming circuit 11 includes a zero-cross detection circuit 15 that detects the polarity of the voltage between the terminals of the resonant capacitor 6 or the resonant inductor 7 and forms a pulse signal from that signal, and A polarity detection circuit 17 for detecting the polarity; and a polarity correction circuit 16 for always obtaining a signal of the same polarity since the output signal of the zero cross detection circuit 15 is inverted when the polarity of the low frequency AC power source 1 is inverted. Consists of.

Further, the second pulse signal is a second pulse signal whose inputs are the output of the polarity correction circuit 16 and the output of the first pulse type control circuit 10.
obtained by the pulse forming circuit 12.

The first pulse and second pulse signal waveforms are input to the multiplexer circuit 13, and according to the polarity of the low frequency power supply 1, when the potential of terminal A is higher than the potential of terminal A, the first pulse signal is input to the multiplexer circuit 13. , the second pulse signal is input to the gate drive circuit 14a, and the second pulse signal is input to the gate drive circuit 14a.
input to b.

Also, when the potential of terminal A is lower than the potential of terminal A,
The multiplexer circuit 13 operates so that the first pulse signal is input to the gate drive circuit 14b and the second pulse signal is input to the gate drive circuit 14a.

FIG. 3 shows a specific example of the embodiment shown in FIG. 2, and FIG. 4 shows voltage and current waveforms at various parts.

Based on these, explanations will be added below.

The voltage between terminals of the switching semiconductor block (hereinafter referred to as ■) is detected from terminal B-A, and when the voltage is sufficient to turn on the vF lightning voltage transistor 811, the transistor 812 is turned on, and then the transistor 816 is turned on. 817
is turned on, and the capacitor 823 is discharged.

The constant of the resistor 820 must be set so that the discharge time constant with the capacitor 823 is sufficiently small.

Even if the polarity of the terminal B-A is reversed, the full-wave bridge circuit of the diodes 803 to 806 is connected to the transistor 811.
This is to turn on the .

In FIG. 4, a is the load high-frequency current waveform, b is the collector voltage waveform of the transistor 812, and C is the capacitor 823.
This is the voltage waveform between the terminals.

When the voltage between the terminals of the capacitor 823 becomes higher than the division ratio voltage of the resistors 824 and 825, the output of the comparator 826 becomes "H", the preset of the flip-flop 828 is activated, and the output Q terminal becomes "H".

The timing of the preset terminal is shown in FIG. 4d.

The voltage across the terminals of the commutation inductance 7 (hereinafter referred to as vL) as shown in g in Fig. 4 is measured from the terminal C by the comparator 1
The polarity is detected at 54.

When the voltage between terminals B and A is reversed, the waveform of (1) is also reversed.

Therefore, from terminal A. , and obtains an output waveform synchronized with the polarity of VIN from the collector of the transistor 176. Then, the collector output of the comparator 154 and the transistor 176 is inputted to the EX-OR gate 16, and the output is sent to the flip-flop 10. Input to the T terminal of.

The waveform becomes the waveform shown in e of FIG. 4 regardless of the VIN polarity.

The outputs of the first pulse forming circuit 10 and the second pulse forming circuit 12, which operate as described above, are transferred to a multiplexer circuit 13.
When terminal A has a higher voltage than terminal A,
The output of the gate 136 is the signal f in FIG. 4, and the output of the gate 137 is the signal i in FIG. The signal i in FIG. 4 is output to the output of the gate 137, and the signal f in FIG. 4 is output to the output of the gate 137.

The timing at which a voltage is applied to the base of the final output transistor 925 of the valley inhibition circuit 9 is shown at 1 in FIG.

VIN zero cross pulse from terminal A (j in Figure 5)
Resistor 914 that sets a certain period of prohibition time based on the waveform
and a capacitor 915, and transistors 916 and 91
9, the prohibited time pulse width is formed.

And at flip-flop 922, zero volt
Performs switching start operation.

Further, the Q output terminal and T input terminal of the clip flop 922 are inputted to a NAND gate 923 to obtain 1 in FIG.

When voltage is applied to the base of transistor 925, capacitor 823 is discharged and no "H" input is applied to the preset terminal of flip-flop 10, resulting in no gate signal being output.

The signals output from 136 and 137 are sent from DC power supply VCC to resistors 142a and 142b and pulse transformer 1.
The series circuit of 43a and 143b is connected to the transistor 144a.
, 144b.
a, 144b.

When transistors 144a and 144b are turned on, IG-I
A gate current flows from the terminal to K or 2G-2, triggering the thyristor 41 or 42.

Then, when the transistor 144a or 144b turns from on to off, the pulse transformer 143a or 14
3b, a reverse bias voltage is applied between the gate and cathode of thyristor 41 and 42, and thyristor 4L4
Ensure turn-off of 2.

As described above, according to the frequency converter of the present invention, it is possible to supply a gate pulse signal of an appropriate width to the thyristor according to the polarity of the low frequency AC power supply, thereby reducing the gate loss of the thyristor and at the same time reducing the power transformer. In addition, by using one pulse transformer for one gate, a stable reverse bias voltage is applied between the gate and cathode of the thyristor, making the switching of the thyristor stable. , it is easy to obtain high-frequency alternating current, and other effects are achieved.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram of the main circuit section of a frequency converter to which the present invention is applied, Fig. 2 is a block diagram of a control circuit of the frequency converter, and Fig. 3 is a circuit diagram of an embodiment of the control circuit. , FIG. 4, and FIG. 5 are voltage waveform diagrams of various parts within the control circuit. 8...First pulse start timing forming circuit, 9
...Valley prohibition circuit, 10...First pulse type warning circuit, 11...First pulse stop timing type warning circuit, 12...Second pulse Formation circuit, 1
3... Multiplexer circuit, 14a, 14b.
... Gate drive circuit, 15 ... Zero cross detection circuit, 16 ... Polarity correction circuit,
17...Polarity detection circuit.

Claims (1)

[Claims] 1. Consists of a frequency conversion circuit that directly converts low-frequency AC into high-frequency AC and its control circuit, and the frequency conversion circuit includes at least one switching semiconductor block capable of bidirectional conduction, a resonant capacitor, and a control circuit thereof. a series resonant circuit including a resonant inductor; A zero-crossing detection circuit that detects zero-crossing of the voltage between the terminals of a capacitor or resonant inductor; a polarity detection circuit that detects the polarity of the low-frequency AC; and a constant pulse always generated in response to fluctuations in the low-frequency AC polarity. a first pulse stop timing circuit that forms a first pulse from the output signals of the first pulse start timing forming circuit and the first pulse stop timing forming circuit; a second pulse forming circuit that forms a second pulse from the output signals of the first pulse forming circuit and the polarity correction circuit;
and a multiplexer circuit which receives the output signals of the first pulse forming circuit and the second pulse forming circuit and outputs a signal to the gate drive circuit according to the low frequency polarity. . 2. The frequency conversion device according to claim 1, wherein the gate drive circuit allows a forward current to flow between the gate and cathode of the switching element, and applies a reverse bias voltage in the opposite direction. 3 A flip-flop is used as the first pulse type control circuit, and the output of the first pulse start timing forming circuit is connected to the set terminal of this flip flop, and then the output of the first pulse stop timing forming circuit is connected to the reset terminal. The frequency conversion device according to claim 1, characterized in that: