JPS5850B2 - Main memory expansion unit access method - Google Patents

Description

[Detailed description of the invention] The present invention relates to an access method for a main memory expansion device.

Conventionally, in main memory expansion methods, especially in minicomputers with a 16-bit word length, the address space (this will be called the logical space) that can be accessed by an instruction is up to 64 words, but the following boundary Due to the address translation mechanism such as register method or mapping method, the main memory address space (this will be called physical space) is 6
It can be extended to more than 4 words.

Below, we will show typical address translation methods.

(1) Boundary register method In this method, as shown in Figure 1, the logical space LOP to which the currently executing program belongs is specified by the logical space number register 11, and accesses are made using address A in the logical space as the boundary. When the logical address a<A, bank number #0 is always selected, and when a>A, the bank number specified by register 11 is selected to expand the physical space PHP of the main memory to 64 words or more. do.

(2) Mapping method In this method, as shown in FIG. 2, the physical space PHP and the logical space LOP are divided into pages of equal capacity, and the mapping mechanism 21 includes the correspondence between the logical page number and the physical page number. By defining the word in the map, words are made to correspond to the expanded main memory in the logical space 64.

By changing the data in the map or having multiple maps, multiple logical spaces are obtained.

In these methods, as shown in Figures 1 and 2, O
If the S (operating system) area and the user area always coexist in one logical space, referencing the user area from the O8 area and vice versa is similar to when the conventional main memory has only 64 words or more. It is also easily possible.

However, due to the increase in capacity associated with the higher functionality of the O8, the user area is relatively reduced, and in some cases it becomes necessary to arrange the O8 area and the user area in completely different logical spaces.

That is, it becomes necessary for a program belonging to a certain logical space to refer to data in another logical space.

The method conventionally used in this case will be explained with reference to FIG.

In this example, data in user area n is referenced from the OS program, and a 0PEN command (open command) is issued each time area n is referenced.

That is, the 0PEN instruction specifies the logical space number n to be referenced, and only the instruction immediately after the 0PEN instruction can refer to the logical space n.

In the figure, the LD instruction (load instruction) and STO instruction (store instruction) correspond to this.

The disadvantage of this method is that it is necessary to issue a 0PEN instruction every time another logical space is referenced, which increases the program capacity and execution time.

In particular, since the user area is frequently referenced from the O8, if the O8 area and the user area cannot coexist in the same logical space, the performance of the O8 will be greatly affected.

The present invention has been made to solve the drawbacks of the conventional methods described above, and its purpose is to provide an access method that facilitates data references between multiple logical spaces obtained by expanded main memory. be.

In order to achieve the above object, the present invention provides a logical space temporary storage register that stores a logical space number, stores a referenced logical space number in the register, and when referencing, reads this logical space number and addresses the address. It is intended to be used for conversion.

According to a preferred embodiment of the present invention, address modification format schemes are actively utilized.

Hereinafter, preferred embodiments of the present invention will be described in detail based on the drawings.

FIG. 4 shows a multi-computer system according to the present invention.

This system includes four processing units 31 to 34, main storage devices 35 to 38 each having its own, and a shared storage management mechanism 39.
, and an inter-processing device shared storage device 40.

In a certain processing device, for example, as shown in FIG. 5, the main memory has a physical space PHP of 0 to 128k, and the physical address space of the shared memory is 256 to 256k in any processing device.
512k.

This physical space is made to correspond to a plurality of logical spaces LOP by the address conversion mechanism 41 using various methods such as the above-mentioned boundary register method and mapping method, and the O8 area is taken as logical space #0.

Next, the access mechanism of the main memory expansion device, which is located in each processing unit in the system shown in FIG. 3 and is the core of the present invention, will be explained in detail using FIG. 6.

This access mechanism is limited to a pace register type data processing device, but this access mechanism temporarily stores logical space numbers corresponding to the instruction register 61 and base register numbers #0 to #7. , a register selection circuit 69 that temporarily stores the logical space number and selects one of the registers 2 to 68 according to the pace register number specified by the base register number designating part bits 5 to 7B of the instruction register 61; The address register 70 specifies the logical address to be referred to within the address register 70, and the address translation mechanism 41 determines a physical address based on the logical space number given by the register selection circuit 69 and the logical address given by the address register 71.

For example, in FIG. 5, a case will be described in which the OS program in logical space #0 is being executed and refers to logical spaces #n1 and O2.

When the OS program is being executed, the logical space numbers are temporarily stored, and all of the distals 2 to 68 are set to the initial state of 0 when the mode is changed from the user mode to the OS mode.

As shown in FIG. 7, from the OS program to the logical space #n
1, a SET command is issued, and the operation of this command will be explained with reference to FIG.

When the instruction in the instruction register 61 is a SET instruction, the base register number specifying unit B of the instruction temporarily stores the logical space numbers corresponding to the base register numbers #0 to #7 via the decoder 81. One of them is selected, and the logical space number n specified by bits 12 to 15 of the instruction register 61 is stored in the selected register.

Therefore, when the SET command shown in FIG. 7A is issued, the logical space number is temporarily stored and the value of distal 2 becomes nl.

From now on, memory reference instructions such as LD instructions and STO instructions (store instructions), and base register instruction modification instructions,
For example, when the LD command shown in FIG. 7 is issued, the base register command part B of the command is 1, so the register selection circuit 69 shown in FIG. logical space number n
1 is read.

As a result, nl, which is different from the logical space number 0 of O8, is given to the address translation mechanism 41, and data reference to logical space #n1 becomes possible.

Furthermore, when the SET command c in FIG. 8 is issued, it becomes possible to reference the logical space n2 with a data reference command whose address is modified in base register #2.

This operation continues until the contents of the logical space number temporary storage register are restored by the SET command.

For example, when the second instruction in FIG. 7 is executed, temporary storage register port 4 (#2) is selected in FIG. 8, and this register stores the logical space number 0, ie, O8.

Therefore, from now on, all reference destinations of data reference instructions whose addresses are modified by base register #2 will be within the logical space of the OS.

As is clear from the above, the logical space is the main memory in Figure 5,
Regardless of whether the shared memory is supported, other logical spaces can be referenced in exactly the same way.

According to the example illustrated above, when an expanded main memory is associated with multiple logical spaces using an address conversion mechanism, data reference from one logical space to another space can be realized using simple hardware. Moreover, since it is only necessary to issue a special instruction at the time of starting reference and the time of ending reference, there is almost no increase in program capacity or execution time.

According to the present invention, when the O8 area and the user area exist in different logical spaces, data reference from the O8 to the user area can be easily performed, and the usable area in the logical space for both the O8 and the user program increases.

[Brief explanation of drawings]

Figures 1 and 2 are diagrams showing the address translation mechanism, Figure 3 is a diagram showing the conventional geological access method, Figure 4 is a diagram of a preferred target example of the present invention, and Figure 5 is a diagram showing spatial mutual access. 6 is a diagram showing an example of the relationship, FIG. 6 is a diagram showing an embodiment of the present invention, FIG. 7 is a diagram showing the method, and FIG. 8 is a diagram showing an example of setting a logical space number. Explanation of symbols 61...Instruction register, 62 to 68
...Logical space number temporary storage register, 69...
... Selection circuit, 7O ... Address register, 41 ... Address conversion mechanism.

Claims (1)

[Scope of Claims] 1. A main memory expansion device that accesses a main memory expansion device that makes the physical address space of the main memory correspond to a plurality of logical address spaces, and performs address conversion between the spaces using an address conversion mechanism. In this access method, one or more logical space number temporary storage registers are provided for storing logical space numbers, the referenced logical space number is temporarily stored in the register, and the temporarily stored interval is At the time of a reference request, the corresponding logical space number located below is read from the corresponding register as the reference destination logical space number, and the read logical space number is sent to the address conversion mechanism. Main memory expansion unit access method. 2. In an access method for a main memory expansion device that makes the physical address space of the main memory correspond to a plurality of logical address spaces, and uses an address conversion mechanism to perform address conversion between the spaces. , one or more logical space number temporary storage registers that are provided corresponding to one or more address modification register numbers given by the instruction register and that store logical space numbers from time to time; and the instruction register. register selection means for selecting one of the logical space number temporary storage registers according to the register number given by the logical space number temporary storage register, and sending the contents of the selected register to the address translation mechanism; An access method for a main memory expansion device, characterized in that by changing the contents of a storage register, it is possible to refer to a logical space designated by the register.