JPS5851289B2 - data transfer device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data transfer device, specifically a data transfer device that transfers data output from a computer to a controlled device via a plurality of serially connected data buses. The purpose of this is to automatically detect a data transfer error when it occurs and notify an error, and also to easily and quickly inform the computer on which data bus the data transfer error occurred. The purpose is to make it detectable.

Generally, when a controlled device is controlled by a computer, data calculated by the computer is given to the controlled device via an interface provided on the computer side and an interface provided on the controlled device side. ing.

Therefore, connection cables are naturally required between computers and interfaces, interfaces and interfaces, and interfaces and controlled equipment, and noise signals induced in these connection cables may be given to the controlled equipment as data. .

If control continues with such erroneous data being given to the controlled device, the controlled device will malfunction, so if erroneous data is transferred, it must be detected as an abnormality.

For this reason, conventionally, the operation of the controlled device is detected and fed back to the computer, and the computer side reads the feedback signal as input data after sending the data, and compares the read signal with the sent data. It was determined whether there was an abnormality or not.

To perform such an operation, it is possible to incorporate the input command and judgment command program after the normal output command program, but if such an operation is performed every time data is sent, the program will only become longer. However, it had the disadvantage that the control speed by the computer was slow.

In addition, with such conventional devices, when a data transfer error occurs, it is impossible to know in which part the transfer error occurred, and there is a problem in that it takes time to discover the abnormal location.

The present invention has been made to eliminate such drawbacks, and for each of a plurality of serially connected data buses, the data output on each data bus is compared with the data received by the receiving means. Comparing means for detecting a data transfer error is provided, and the plurality of comparing means are operated in sequence in response to each of a plurality of output signals outputted from the computer in response to execution of different output commands. The present invention is characterized in that a data bus on which a transfer error has occurred can be identified based on which output instruction execution time the data transfer error was detected.

First, a circuit for detecting a data transfer error on a single data bus will be described.

In Figure 1, 1 is a computer, 2 is a computer 1
An interface 3 provided on the side is an interface provided on the controlled equipment 4 side, and intermittent data outputted from the computer 1 is given to the interface 2 via the data bus DB1.

This interface 2 stores intermittent data sent from the computer 1 and outputs it as continuous data, and this continuous data is given to the controlled device side interface 3 via the data bus DB2. .

The controlled device side interface 3 is composed of, for example, a buffer amplifier 30 and an AD converter 31, and converts data applied via the data bus DB2 into an analog signal and provides it to the controlled device 4.

Thereby, the controlled device 4 is controlled based on the data sent from the computer 1.

The computer 1 mainly includes a program counter 10, a memory 11 . Instruction decoder 12, arithmetic unit 1
3. It is composed of an output register 14, and when one address of the memory 11 is designated by the program counter 10, the program stored at the designated address is read out.

The read program is decoded by the instruction decoder 12, and if the read program is an output instruction, an output signal DOA is output.

This output signal DOA is connected to the arithmetic unit 13 and the AND gate AG1.
When the output signal DOA is applied to the arithmetic unit 13, the arithmetic unit 13 outputs control data based on the calculation result and is applied to the output register 14.

Further, a signal IRQ is applied to the AND gate AG1 from a timing signal generation circuit (not shown) between CL6 and CLIO of the execution cycle as shown in FIG. Signal IRQ
is applied, the output signal DOA sent from the instruction decoder 12 is applied to the interface 2.

When the output register 14 receives load signals LO and AD from a timing signal generation circuit (not shown) at the timing of the execution cycle CL6 as shown in FIG.
This output register 1 reads the data output from 3, stores it temporarily, and outputs this stored data.
The data output from 4 is connected to the data bus DB via a gate G, which will be described later.

is output to and given to interface 2.

This interface 2 is mainly a buffer amplifier 20.22
and a reception register 21, and data output from the computer 1 is given to the reception register 21 via a buffer amplifier 20.

This receiving register 21 receives the output signal DO from the computer.
When A is given, the data given by the computer 1 is read and stored, and this stored data is output to the data bus via the buffer amplifier 22 and given to the interface 3.

Furthermore, the computer 1 and the interface 2 are provided with a circuit for detecting an abnormality in data transfer, which is a feature of the present invention. It is composed of AG2, a flip-flop FF, a timer 23 provided in the interface 2, a one-shot circuit 24, and a gate G2.

The timer 23 receives the output signal D output from the computer 1.
When the timer 23, which is activated by the OA, times out, the one-shot circuit 24 outputs an echo back signal EB with a fixed time width tw.

This echo back signal EB is applied to the gate G2 and the AND gate AG2, and is applied to the gate G1 via the inverter INV.

Therefore, the gate G is open until the output signal DOA is sent out from the computer 1, and when the echo back signal EB is sent out after a certain period of time after the output signal DOA is sent out from the computer 1, the gate G1 is closed. Gate G2 is opened.

As a result, the data output from the reception register 21 is fed back to the data bus DB via the gate G2.

The comparator 16 compares the data output from the output register 14 and the data output to the data bus DB1, and if the two do not match, a mismatch signal DI is output.
F is output and applied to one input terminal of AND gate AG2.

Moreover, since the echo back signal EB is applied to the other input terminal of this AND gate AG2 as described above, this AND gate AG2 is operated while the echo back signal EB is being output, that is, the receiving register It is opened only while the data received by the comparator 21 is being output to the data bus DB1, and the discrepancy signal DIF output from the comparator 16 is applied to the set terminal S of the flip-flop FF.

This flip-flop FF is set and memorized when the mismatch signal DIF is given to the set terminal S. When set, the abnormal signal ERRO is output from the output terminal Q.
R is transmitted and an abnormality is notified by an abnormality alarm (not shown).

Further, the output terminal Q of this flip-flop FF is an ant game I which controls the step signal of the program counter 10.
-AG3, and if an abnormality occurs, this AND gate AG3 is closed to stop the program counter 10 from advancing.

As a result, control of the controlled device 4 by the computer 1 is stopped, thereby preventing the controlled device 4 from malfunctioning.

Next, the operation of the data transfer device based on the above-mentioned interception will be explained.

Assuming that operation of the computer 1 is started by a start switch (not shown), the program at the address specified by the program counter 10 is read out from the memory 11 at the timing of the read cycle CL2 shown in FIG.

The read program is decoded by the instruction decoder 12 at the timing of CL4, and if the decoded program is an output instruction, an output signal DOA is sent out from the arithmetic unit 13 to the output register 1.
Control data is given to 4.

When the read cycle ends in this way and the execution cycle begins, the load signal LOAD is applied to the output register 14 at the timing of CL5.

As a result, the output register 14 reads the data output from the arithmetic unit 13, temporarily stores it, and outputs the stored data.

At this time, since the signal IRQ has not yet been sent out, the output signal DOA is not given to the interface 2, and the echo back signal EB is not sent out either.

Therefore, gate G remains open, and the data output from output register 14 is gate G-1.
-G, data bus DB, is applied to the reception register 21 via the buffer amplifier 20.

Then, when the signal IRQ is applied to the analog gate (AG) at the timing of CL6, the output signal DOA is applied to the receiving register 21, so that the data output from the output register 14 is read by the receiving register 21.

This read data is then sent to the buffer amplifier 22,
The signal is applied to the interface 3 via the data bus DB2, and a signal corresponding to the data is applied to the controlled device 4.

When the output signal DOA is output from the computer 1, this output signal DOA is also given to the timer 23, so the timer 23 is activated.

When the timer 23 times out after the set time ts has elapsed, the one-shot circuit 23 outputs a second
An echo back signal FB having a time width tw as shown in FIG. d is sent out.

Note that the set time ts of the timer 23 may be set longer than the time for the reception register 21 to finish reading data, and the time width tw of the echo back signal BB is necessary for the comparator 16 to determine whether the data match. The length of time should be longer than that.

When the echo back signal EB is sent out, the gate G1 is closed as described above, and the gate G2 and the AND gate AG2 are closed.
will be held.

As a result, data sent from the reception register 21 is provided to the comparator 16 via the gate G2 and the data bus DB1.

At this time, if there is no abnormality in the transferred data, the comparator 16
The discrepancy signal DIF is not output from then on, and the program counter 10 advances to execute the next program.

However, if a noise voltage is induced in the data bus DB1 or the buffer amplifier 20, reception register 21, etc. fail, the data sent from the output register 14 and the reception register 21
If the data being sent out are different, this is determined by the comparator 16, and the comparator 16 outputs a discrepancy signal DIF as shown in FIG. 2e.

This mismatch signal DIF is then applied to flip-flop FF via AND gate AG2 to set flip-flop FF.

As a result, the program counter 10 stops advancing, and the control of the controlled device 4 is stopped.

Further, an abnormality is notified by an abnormality notification circuit (not shown).

Embodiments of the present invention will be described above based on the drawings.

In FIG. 3, the computer 1 has almost the same configuration as that shown in FIG. 1, but the interface 2 includes a gate G3 and a , an inverter ■N■2 that inverts the echo back signal EB applied from the interface 3 and applies it to the gate G3, and a comparator 25 that compares the data output from the reception register 21 and the data output to the data bus DB2. , an AND gate AG4 is provided that makes the comparator 25 valid only when transmitting an echo back signal.

The interface 3 also includes a reception register 32 that reads and stores data output from the interface 2 when the output signal DOB is applied from the computer 1, and outputs the stored data, and a reception register 32 that is activated by the output signal DOB. a timer 33, a one-shot circuit 34 which is activated by the time-up of this timer 33 and sends out an echo back signal EB of a fixed time width, and a one-shot circuit 34 which is opened by this echo back signal EB and receives the data output from the receiving register 32. A gate G4 for feeding back to the data bus DB2 is added.

Further, the echo back signal EB sent from the one-shot circuit 34 is sent to the inverter INV2 of the interface 2.
and is also given to AND gate AG4.

Therefore, when the output signal DOB is sent from the computer 1 while data is being applied from the interface 2 to the interface 3, the applied data is read into the reception register 32 and the timer 33 is activated.

When this timer 33 is activated, the echo back signal EB is sent out after a certain period of time has elapsed, so that the gate G3 is closed and the gate G4 is opened, and the data read by the receiving register 32 is sent to the gate G4. It is fed back to the data bus DB2 via the data bus DB2.

As a result, the data sent from the reception register 21 of the interface 2 and the reception register 3 of the interface 3 are
The comparator 25 compares the data read by the comparator 25 with the data read by the comparator 25.

If an abnormality occurs in data transfer between interface 2 and interface 3, and the sent data and received data are different, this is determined by comparator 25, and a discrepancy signal DIF is sent to the computer via AND gate AG4. 1.

Since the discrepancy signal DIF sent to the computer 1 is applied to the set terminal S of the flip-flop FF via the OR gate OR, the flip-flop FF is set and the progress of the program counter 10 is stopped. An abnormality will be reported as soon as the error occurs.

As described above, in this embodiment, when the output signal DOA is output from the computer 1, data is transferred from the computer 1 to the interface 2, and an abnormality in data transfer that has occurred during this time is detected, and the output signal DOB is When the data is output, the data is transferred from interface 2 to interface 3, and any abnormality in data transfer that occurs during this time is detected.

Therefore, by programming the output command DOB after the output command DOA, data transfer to the computer 1 interface 2 and abnormality check, and data transfer from interface 2 to interface 3 and abnormality check will be automatically performed. It will be done.

Even if a data transfer error occurs, if you check from the contents of the program counter 10 whether it stopped after the output command DOA was executed or whether it stopped after the output command DOB was executed, you can check the data transfer. It can be immediately determined whether the abnormality has occurred between the computer 1 and the interface 2 or between the interfaces 2 and 3, and the time required to detect the abnormality can be significantly shortened.

Note that if a large number of interfaces are connected to the computer 1 and you want to automatically detect which interface is abnormal, provide a register corresponding to each interface in the computer 1 and register the discrepancy sent from each interface. The signal DIF may be stored and the contents of the register may be searched by the abnormality detection program without stopping the program counter 10.

As described above, in the present invention, for each of a plurality of serially connected data buses, the data is determined by comparing the data output on each data bus with the data received by the receiving means. In addition to providing comparison means for detecting transfer errors, the plurality of comparison means are activated in sequence in response to each of the plurality of output signals output from the computer in response to the execution of different output commands. Depending on whether a transfer error is detected at the time an output command is executed, the data bus on which the transfer error occurred can be easily identified, which has the advantage of allowing abnormalities to be discovered in a short time.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a data transfer device designed to detect a transfer error on a single data bus, FIG. 2 is a diagram showing the timing of each signal in FIG. 1, and FIG. 3 is an implementation of the present invention. FIG. 2 is a block diagram illustrating an example. 1... Computer, 2, 3... Interface, 14... Output register, 16, 2
5... Comparator, 2L32... Reception register, 23, 33... Timer, 24, 34...
...One-shot circuit, AGl, AG2. AG3
．． AG4...and gate, FF...
Flip-flop, G1. G2. G3. G4...
・Gate, ■N■, ■N■2...Inverter.

Claims (1)

[Claims] 1. In a data transfer device configured to transfer data output from a computer to a controlled device via a plurality of serially connected data buses, each data A data output means connected to the starting end of the bus and outputting the data to be transferred to the data bus; a data receiving means connected to the rear end of each data bus receiving the data sent to the data bus; Comparing means for comparing the received data and the data output from the data output means and transmitting a signal if they do not match, and
control for sequentially enabling a plurality of comparison means provided corresponding to each of the plurality of data buses in response to each of a plurality of output signals output from the computer at different timings by executing different output instructions; and storage means for storing a signal outputted from any one of the plurality of comparison means and transmitting an abnormality signal to the computer.