JPS5851294B2 - Multiprocessor control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a multiprocessor control method for controlling occupancy of a common bus by each processor in a multiprocessor using a plurality of microprocessors.

In a multiprocessor system where multiple microprocessors share a common bus and shared memory connected to it, only one microprocessor can occupy the common bus at the same time, so it is necessary to control the use of the common bus. There is.

Conventionally, in such a multiprocessor control method, the phase of the clock signal is divided into the same number of processors, and each processor can use a common bus only during the period of the clock phase assigned to that processor in a time-sharing manner. Multiprocessor control method % formula % In this multiprocessor control method, each processor can use a common bus every clock period, so
This has the advantage that there is no waiting time for bus use.

However, as the number of processors increases, the time allotted to each processor becomes shorter, so it is necessary to increase the transfer speed of the bus, and the interface between the bus and the processors becomes more complex.

The present invention attempts to eliminate these drawbacks of the prior art, and its purpose is to eliminate the need to increase the bus transfer speed, simplify the interface between the common bus and multiprocessors, and reduce the hardware configuration. The objective is to provide a simple multiprocessor control method.

In order to achieve this object, the multiprocessor control system of the present invention receives a bus use request signal from the processor in a multiprocessor system in which two or more processors operating on a two-phase clock are connected via a common bus. a bus control circuit that sends a bus use permission signal to the processor if the common bus is available; a reference clock generator that generates a reference two-phase clock; In addition, each processor is provided with a shared memory that can be accessed in common from the bus control circuit, and the reference clock is used as a bus request signal in order to temporarily stop the execution of the corresponding processor if a bus permission signal is not obtained from the bus control circuit. It is characterized in that each processor is provided with a clock control circuit that maintains the polarity at the time of generation and otherwise inputs the reference clock directly to the corresponding processor, thereby controlling the occupancy of the common bus by each processor.

Examples will be described below.

FIG. 1 is a block diagram showing the configuration of an embodiment of the multiprocessor control system of the present invention.

In the figure, 1-1tl-2+..., 1-n are processing units (CPUs), 2 is a bus control circuit, 3 is a reference clock generator, 4 is a common bus, and 5 is a shared memory.

Also ILl, IL2. ..., 11-n is a microprocessor, 12-1.12-2. ..., 12-n is a clock control circuit.

FIG. 2 is a time chart showing signals of various parts in the multiprocessor control system shown in FIG.

In the figure, a, I) are reference two-phase clock signals φa31φb8 . c is a common bus use request signal RQi for each processor, d is a bus use permission signal GJ from the bus control circuit 2 to each processor, e is a phase φai at which each processor outputs an address signal, and f is a phase at which each processor transfers data. The phase φbi is changed.

In an arbitrary 1st (i=1 to n) processing device 1-i in FIG. 1, the processor 11-1 outputs an address signal at the phase of the clock signal φai of the corresponding clock control circuit 12-1, and It is assumed that a processor operates with a two-phase clock that transfers data in accordance with the phase of signal φbi.

In FIG. 2, e and f are driven by two-phase clocks φ2iyφ,i, and each clock φai and φbi have a phase difference of 1800 degrees.

Now, when the i-th processor 11-i wishes to use the shared memory 5 connected to the common bus 4, it outputs a common bus use request signal RQi to the bus control circuit 2.

In FIG. 2, C indicates the common bus use request signal RQi, which is delayed by a time τ from the phase of the reference clock φb8.

Here, it is the delay time of a decoder provided in the CPU (not shown) for sending out a common bus use request signal.

On the other hand, when the common bus 4 is available, the bus control circuit 2 outputs a bus use permission signal GRi to the i-th processor.

In FIG. 2, d indicates the bus use permission signal GRi output in this manner.

When the clock control circuit 12-i receives the bus use permission signal GRi, the clock control circuit 12-i outputs the reference clock φa8. of the reference clock generator 3. φb8 is directly output to the processor 11-i as clocks φai and φbi.

Processor 11-1 accesses shared memory 5 in this cycle.

In FIG. 2, numerals 11 and 13 indicate such timing positions.

Even if the common bus use request signal is issued, if the bus use permission signal cannot be obtained because the common bus is in use or for some other reason, the clocks φai and φbi maintain the phase of the reference clock φa3jφb8 when the common bus use request signal was generated. and enters a waiting state.

In FIG. 2, t2 indicates such a timing position.

In other words, when each processor uses shared memory, it outputs a common bus use permission signal to the bus control circuit, and accesses the shared memory after obtaining the bus use permission signal, but multiple processors simultaneously output the common bus use permission signal. If this is output, only one processor to which the common bus usage permission signal has been accepted can access the shared memory, and other processors cannot use the common bus, so execution must be temporarily halted. Therefore, the above-mentioned control is performed.

FIG. 3 is a circuit diagram showing the configuration of one embodiment of the clock control circuit in FIG. 1.

In the figure, 21 is a NAND circuit, and 22 is a flip-flop.

In FIG. 3, the flip-flop 22 has the output of the NAND circuit 21 applied to the preset terminal PR, the reference clock φb8 applied to the clear terminal CLR, the clock φbi from the output Q, and the clock φai from the output Q.
It is configured to output .

In FIG. 3, the NAND circuit 21 has a clock φb8.
, the addition signal (RQi+GRi) of the common bus use request signal and the bus use permission signal is added, and the addition signal (π
Qi+GRi) is "1'', clock φai goes to "0" level and clock φbi goes to 1" at the rising edge of clock φb8, and φai goes to "1" at the falling edge of clock φb8.
'' level, φbi becomes O''' level.

Further, when the addition signal (RQi+GRi) is '0'', the polarities of the clocks φai and φbi are maintained as they are.

In this way, the clock φai+ in each processor
Since the phase of φbi is controlled, if another processor is using the common bus when a processor issues a usage request, the processor that issues the usage request later can change the reference clock phase at the time the common bus usage request signal is generated. Since the processor is held and temporarily stops operating to enter a wait state, a plurality of processors can use the shared memory via a common bus.

In other words, in the conventional multiprocessor control method,
The usage time of the common bus is divided and given to each processor, so there is a need to speed up data transfer on the common bus.

However, in the method of the present invention, the usage time of each processor is not fixedly allocated, and if the common bus is free when a usage request is issued, it can be used immediately, and if it is used by another processor, it can be used immediately. I'm trying to make them wait until then.

So shared memo +7? On the other hand, the transfer speed of input/output data is constant regardless of the number of processors, so there is no need to increase the speed of data transfer on the common bus.

As explained above, according to the multiprocessor control method of the present invention, there is no need to increase the bus transfer speed in a multiprocessor system in which a plurality of microprocessors share a common bus and a shared memory connected to the common bus. Moreover, the interface between the common bus and the multiprocessors is simple, and a multiprocessor control system with a simple hardware configuration can be realized, resulting in excellent effects.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the multiprocessor control method of the present invention, FIG. 2 is a time chart showing various signals in the multiprocessor control method of FIG. 1, and FIG. 3 is a clock control circuit diagram. FIG. 2 is a circuit diagram showing the configuration of an embodiment. Ll, L2. ...'l-n: Processing unit (CPU), 2:
Bus control circuit, 3: Reference clock generator, 4: Common bus, 5: Shared memory, 11□, IL2. ...11-n:
Microprocessor, 12-1.12-2゜...-,1
1n: clock control circuit, 21: NAND circuit, 22: flip-flop.

Claims (1)

[Claims] In a multiprocessor system in which two or more processors operating on a 12-sum clock are connected via a common bus, when a bus use request signal is received from a processor, if the common bus can be used, a bus use permission signal is sent to the processor. A bus control circuit for sending data to the processor, a reference clock generator for generating a reference two-phase clock, and a shared memory connected to a common bus and commonly accessible from each processor via the common bus are provided in common for each processor. , if a bus use permission signal cannot be obtained from the bus control circuit, the reference clock is set to the polarity 1 when the bus use request signal is generated in order to temporarily stop the execution of the corresponding processor. A multiprocessor control system characterized in that each processor is provided with a clock control circuit that maintains a clock and inputs a reference clock directly to the corresponding processor in other cases, thereby controlling the occupancy of a common bus by each processor.